Initial commit

Experiments/Exp1/Exp1.srcs/sim_1/new/tb_exp1.v

@@ -0,0 +1,48 @@
+`timescale 1ns / 1ps
+module tb_exp1;
+
+    reg  [31:0] alu_a, alu_b;
+    reg  [2:0]  AluCtrl;
+    wire [31:0] AddResult;
+    wire        Zero;
+
+    reg  [31:0] Ext_DataIn;
+    reg  [1:0]  ExtOp;
+    wire [31:0] Ext_DataOut;
+
+    ALU u_ALU (
+        .a(alu_a), .b(alu_b), .AluCtrl(AluCtrl),
+        .AddResult(AddResult), .Zero(Zero)
+    );
+
+    Ext u_Ext (
+        .DataIn(Ext_DataIn), .ExtOp(ExtOp), .DataOut(Ext_DataOut)
+    );
+
+    initial begin
+        $display("----------------- 开始实验一仿真 -----------------");
+        $display("=========== 测试 ALU 模块 ===========");
+        alu_a = 32'd10; alu_b = 32'd5; AluCtrl = 3'b000; #10;
+        $display("ALU ADD: %d + %d = %d", alu_a, alu_b, AddResult);
+        alu_a = 32'd10; alu_b = 32'd10; AluCtrl = 3'b001; #10;
+        $display("ALU SUB: %d - %d = %d, Zero = %b", alu_a, alu_b, AddResult, Zero);
+        alu_a = 32'hFFFFFFFF;
+        alu_b = 32'd1;
+        AluCtrl = 3'b101; #10;
+        $display("ALU SLT: $signed(%h) < $signed(%h) is %d", alu_a, alu_b, AddResult);
+        AluCtrl = 3'b110; #10;
+        $display("ALU SLTU: %h < %h is %d", alu_a, alu_b, AddResult);
+
+        $display("\n=========== 测试 Ext 模块 ===========");
+        Ext_DataIn = 32'h02A4C503;
+        ExtOp = 2'b00; #10;
+        $display("ExtOp=00, DataIn=%h, DataOut=%h (符号扩展[21:10])", Ext_DataIn, Ext_DataOut);
+        ExtOp = 2'b01; #10;
+        $display("ExtOp=01, DataIn=%h, DataOut=%h (符号扩展[25:10] << 2)", Ext_DataIn, Ext_DataOut);
+        ExtOp = 2'b10; #10;
+        $display("ExtOp=10, DataIn=%h, DataOut=%h ([24:5] << 12)", Ext_DataIn, Ext_DataOut);
+        
+        $display("\n----------------- 实验一仿真结束 -----------------");
+        $stop;
+    end
+endmodule