Initial commit
This commit is contained in:
1
Experiments/Exp4/Exp4.ip_user_files/README.txt
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1
Experiments/Exp4/Exp4.ip_user_files/README.txt
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The files in this directory structure are automatically generated and managed by Vivado. Editing these files is not recommended.
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71
Experiments/Exp4/Exp4.sim/sim_1/behav/xsim/glbl.v
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71
Experiments/Exp4/Exp4.sim/sim_1/behav/xsim/glbl.v
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// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
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`ifndef GLBL
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`define GLBL
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`timescale 1 ps / 1 ps
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module glbl ();
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parameter ROC_WIDTH = 100000;
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parameter TOC_WIDTH = 0;
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//-------- STARTUP Globals --------------
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wire GSR;
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wire GTS;
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wire GWE;
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wire PRLD;
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tri1 p_up_tmp;
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tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
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wire PROGB_GLBL;
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wire CCLKO_GLBL;
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wire FCSBO_GLBL;
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wire [3:0] DO_GLBL;
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wire [3:0] DI_GLBL;
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reg GSR_int;
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reg GTS_int;
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reg PRLD_int;
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//-------- JTAG Globals --------------
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wire JTAG_TDO_GLBL;
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wire JTAG_TCK_GLBL;
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wire JTAG_TDI_GLBL;
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wire JTAG_TMS_GLBL;
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wire JTAG_TRST_GLBL;
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reg JTAG_CAPTURE_GLBL;
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reg JTAG_RESET_GLBL;
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reg JTAG_SHIFT_GLBL;
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reg JTAG_UPDATE_GLBL;
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reg JTAG_RUNTEST_GLBL;
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reg JTAG_SEL1_GLBL = 0;
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reg JTAG_SEL2_GLBL = 0 ;
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reg JTAG_SEL3_GLBL = 0;
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reg JTAG_SEL4_GLBL = 0;
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reg JTAG_USER_TDO1_GLBL = 1'bz;
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reg JTAG_USER_TDO2_GLBL = 1'bz;
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reg JTAG_USER_TDO3_GLBL = 1'bz;
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reg JTAG_USER_TDO4_GLBL = 1'bz;
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assign (strong1, weak0) GSR = GSR_int;
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assign (strong1, weak0) GTS = GTS_int;
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assign (weak1, weak0) PRLD = PRLD_int;
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initial begin
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GSR_int = 1'b1;
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PRLD_int = 1'b1;
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#(ROC_WIDTH)
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GSR_int = 1'b0;
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PRLD_int = 1'b0;
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end
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initial begin
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GTS_int = 1'b1;
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#(TOC_WIDTH)
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GTS_int = 1'b0;
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end
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endmodule
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`endif
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11
Experiments/Exp4/Exp4.sim/sim_1/behav/xsim/tb_exp4.tcl
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11
Experiments/Exp4/Exp4.sim/sim_1/behav/xsim/tb_exp4.tcl
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@@ -0,0 +1,11 @@
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set curr_wave [current_wave_config]
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if { [string length $curr_wave] == 0 } {
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if { [llength [get_objects]] > 0} {
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add_wave /
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set_property needs_save false [current_wave_config]
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} else {
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send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
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}
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}
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run 1000ns
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16
Experiments/Exp4/Exp4.sim/sim_1/behav/xsim/tb_exp4_vlog.prj
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16
Experiments/Exp4/Exp4.sim/sim_1/behav/xsim/tb_exp4_vlog.prj
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# compile verilog/system verilog design source files
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verilog xil_defaultlib \
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"../../../../../Shared/ALU.v" \
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"../../../../../Shared/Controller.v" \
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"../../../../../Shared/DataRAM.v" \
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"../../../../../Shared/Datapath.v" \
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"../../../../../Shared/Ext.v" \
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"../../../../../Shared/LA32R_CPU.v" \
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"../../../../../Shared/Registers.v" \
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"../../../../Exp4.srcs/sim_1/new/tb_exp4.v" \
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# compile glbl module
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verilog xil_defaultlib "glbl.v"
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# Do not sort compile order
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nosort
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12
Experiments/Exp4/Exp4.sim/sim_1/behav/xsim/webtalk.jou
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12
Experiments/Exp4/Exp4.sim/sim_1/behav/xsim/webtalk.jou
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#-----------------------------------------------------------
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# Webtalk v2018.1 (64-bit)
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# SW Build 2188600 on Wed Apr 4 18:40:38 MDT 2018
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# IP Build 2185939 on Wed Apr 4 20:55:05 MDT 2018
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# Start of session at: Thu Jul 3 05:15:51 2025
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# Process ID: 26536
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# Current directory: D:/Schoolwork/ComputerComposition/Experiments/Exp4/Exp4.sim/sim_1/behav/xsim
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# Command line: wbtcv.exe -mode batch -source D:/Schoolwork/ComputerComposition/Experiments/Exp4/Exp4.sim/sim_1/behav/xsim/xsim.dir/tb_exp4_behav/webtalk/xsim_webtalk.tcl -notrace
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# Log file: D:/Schoolwork/ComputerComposition/Experiments/Exp4/Exp4.sim/sim_1/behav/xsim/webtalk.log
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# Journal file: D:/Schoolwork/ComputerComposition/Experiments/Exp4/Exp4.sim/sim_1/behav/xsim\webtalk.jou
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#-----------------------------------------------------------
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source D:/Schoolwork/ComputerComposition/Experiments/Exp4/Exp4.sim/sim_1/behav/xsim/xsim.dir/tb_exp4_behav/webtalk/xsim_webtalk.tcl -notrace
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@@ -0,0 +1,12 @@
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#-----------------------------------------------------------
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# Webtalk v2018.1 (64-bit)
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# SW Build 2188600 on Wed Apr 4 18:40:38 MDT 2018
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# IP Build 2185939 on Wed Apr 4 20:55:05 MDT 2018
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# Start of session at: Wed Jul 2 00:40:08 2025
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# Process ID: 26240
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# Current directory: D:/Schoolwork/ComputerComposition/Experiments/Exp4/Exp4.sim/sim_1/behav/xsim
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# Command line: wbtcv.exe -mode batch -source D:/Schoolwork/ComputerComposition/Experiments/Exp4/Exp4.sim/sim_1/behav/xsim/xsim.dir/tb_exp4_behav/webtalk/xsim_webtalk.tcl -notrace
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# Log file: D:/Schoolwork/ComputerComposition/Experiments/Exp4/Exp4.sim/sim_1/behav/xsim/webtalk.log
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# Journal file: D:/Schoolwork/ComputerComposition/Experiments/Exp4/Exp4.sim/sim_1/behav/xsim\webtalk.jou
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#-----------------------------------------------------------
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source D:/Schoolwork/ComputerComposition/Experiments/Exp4/Exp4.sim/sim_1/behav/xsim/xsim.dir/tb_exp4_behav/webtalk/xsim_webtalk.tcl -notrace
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@@ -0,0 +1,12 @@
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#-----------------------------------------------------------
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# Webtalk v2018.1 (64-bit)
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# SW Build 2188600 on Wed Apr 4 18:40:38 MDT 2018
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# IP Build 2185939 on Wed Apr 4 20:55:05 MDT 2018
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# Start of session at: Wed Jul 2 00:39:32 2025
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# Process ID: 26568
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# Current directory: D:/Schoolwork/ComputerComposition/Experiments/Exp4/Exp4.sim/sim_1/behav/xsim
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# Command line: wbtcv.exe -mode batch -source D:/Schoolwork/ComputerComposition/Experiments/Exp4/Exp4.sim/sim_1/behav/xsim/xsim.dir/tb_exp4_behav/webtalk/xsim_webtalk.tcl -notrace
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# Log file: D:/Schoolwork/ComputerComposition/Experiments/Exp4/Exp4.sim/sim_1/behav/xsim/webtalk.log
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# Journal file: D:/Schoolwork/ComputerComposition/Experiments/Exp4/Exp4.sim/sim_1/behav/xsim\webtalk.jou
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#-----------------------------------------------------------
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source D:/Schoolwork/ComputerComposition/Experiments/Exp4/Exp4.sim/sim_1/behav/xsim/xsim.dir/tb_exp4_behav/webtalk/xsim_webtalk.tcl -notrace
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@@ -0,0 +1,12 @@
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#-----------------------------------------------------------
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# Webtalk v2018.1 (64-bit)
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# SW Build 2188600 on Wed Apr 4 18:40:38 MDT 2018
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# IP Build 2185939 on Wed Apr 4 20:55:05 MDT 2018
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# Start of session at: Thu Jul 3 05:13:39 2025
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# Process ID: 33472
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# Current directory: D:/Schoolwork/ComputerComposition/Experiments/Exp4/Exp4.sim/sim_1/behav/xsim
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# Command line: wbtcv.exe -mode batch -source D:/Schoolwork/ComputerComposition/Experiments/Exp4/Exp4.sim/sim_1/behav/xsim/xsim.dir/tb_exp4_behav/webtalk/xsim_webtalk.tcl -notrace
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# Log file: D:/Schoolwork/ComputerComposition/Experiments/Exp4/Exp4.sim/sim_1/behav/xsim/webtalk.log
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# Journal file: D:/Schoolwork/ComputerComposition/Experiments/Exp4/Exp4.sim/sim_1/behav/xsim\webtalk.jou
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#-----------------------------------------------------------
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source D:/Schoolwork/ComputerComposition/Experiments/Exp4/Exp4.sim/sim_1/behav/xsim/xsim.dir/tb_exp4_behav/webtalk/xsim_webtalk.tcl -notrace
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BIN
Experiments/Exp4/Exp4.sim/sim_1/behav/xsim/xelab.pb
Normal file
BIN
Experiments/Exp4/Exp4.sim/sim_1/behav/xsim/xelab.pb
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Binary file not shown.
@@ -0,0 +1 @@
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-wto "ae2a6b03df4749b48fa62497cdcfc9a7" --incr --debug "typical" --relax --mt "2" -L "xil_defaultlib" -L "unisims_ver" -L "unimacro_ver" -L "secureip" --snapshot "tb_exp4_behav" "xil_defaultlib.tb_exp4" "xil_defaultlib.glbl" -log "elaborate.log"
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@@ -0,0 +1 @@
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Breakpoint File Version 1.0
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@@ -0,0 +1,144 @@
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/**********************************************************************/
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/* ____ ____ */
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/* / /\/ / */
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/* /___/ \ / */
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/* \ \ \/ */
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/* \ \ Copyright (c) 2003-2013 Xilinx, Inc. */
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/* / / All Right Reserved. */
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/* /---/ /\ */
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/* \ \ / \ */
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/* \___\/\___\ */
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/**********************************************************************/
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#include "iki.h"
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#include <string.h>
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#include <math.h>
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#ifdef __GNUC__
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#include <stdlib.h>
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#else
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#include <malloc.h>
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#define alloca _alloca
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#endif
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/**********************************************************************/
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/* ____ ____ */
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||||
/* / /\/ / */
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||||
/* /___/ \ / */
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||||
/* \ \ \/ */
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||||
/* \ \ Copyright (c) 2003-2013 Xilinx, Inc. */
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/* / / All Right Reserved. */
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||||
/* /---/ /\ */
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/* \ \ / \ */
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/* \___\/\___\ */
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/**********************************************************************/
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#include "iki.h"
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#include <string.h>
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#include <math.h>
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#ifdef __GNUC__
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#include <stdlib.h>
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#else
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#include <malloc.h>
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#define alloca _alloca
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#endif
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typedef void (*funcp)(char *, char *);
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extern int main(int, char**);
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extern void execute_15(char*, char *);
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extern void execute_16(char*, char *);
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extern void execute_47(char*, char *);
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extern void execute_48(char*, char *);
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extern void execute_49(char*, char *);
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extern void execute_50(char*, char *);
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extern void execute_51(char*, char *);
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extern void execute_52(char*, char *);
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extern void execute_53(char*, char *);
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extern void execute_40(char*, char *);
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extern void execute_41(char*, char *);
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extern void execute_42(char*, char *);
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extern void execute_43(char*, char *);
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extern void execute_44(char*, char *);
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extern void execute_45(char*, char *);
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extern void execute_46(char*, char *);
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extern void execute_4(char*, char *);
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extern void execute_21(char*, char *);
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extern void execute_22(char*, char *);
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extern void execute_30(char*, char *);
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extern void execute_33(char*, char *);
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extern void execute_34(char*, char *);
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extern void execute_35(char*, char *);
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extern void execute_36(char*, char *);
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extern void execute_37(char*, char *);
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extern void execute_38(char*, char *);
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extern void execute_39(char*, char *);
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extern void execute_7(char*, char *);
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extern void execute_8(char*, char *);
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extern void execute_23(char*, char *);
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extern void execute_24(char*, char *);
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extern void execute_10(char*, char *);
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extern void execute_25(char*, char *);
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extern void execute_26(char*, char *);
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extern void execute_27(char*, char *);
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extern void execute_28(char*, char *);
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extern void vlog_simple_process_execute_0_fast_no_reg_no_agg(char*, char*, char*);
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extern void execute_12(char*, char *);
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extern void execute_14(char*, char *);
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extern void execute_31(char*, char *);
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extern void execute_32(char*, char *);
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extern void execute_18(char*, char *);
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extern void execute_19(char*, char *);
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extern void execute_20(char*, char *);
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extern void execute_54(char*, char *);
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extern void execute_55(char*, char *);
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extern void execute_56(char*, char *);
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extern void execute_57(char*, char *);
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extern void execute_58(char*, char *);
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extern void vlog_transfunc_eventcallback(char*, char*, unsigned, unsigned, unsigned, char *);
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funcp funcTab[50] = {(funcp)execute_15, (funcp)execute_16, (funcp)execute_47, (funcp)execute_48, (funcp)execute_49, (funcp)execute_50, (funcp)execute_51, (funcp)execute_52, (funcp)execute_53, (funcp)execute_40, (funcp)execute_41, (funcp)execute_42, (funcp)execute_43, (funcp)execute_44, (funcp)execute_45, (funcp)execute_46, (funcp)execute_4, (funcp)execute_21, (funcp)execute_22, (funcp)execute_30, (funcp)execute_33, (funcp)execute_34, (funcp)execute_35, (funcp)execute_36, (funcp)execute_37, (funcp)execute_38, (funcp)execute_39, (funcp)execute_7, (funcp)execute_8, (funcp)execute_23, (funcp)execute_24, (funcp)execute_10, (funcp)execute_25, (funcp)execute_26, (funcp)execute_27, (funcp)execute_28, (funcp)vlog_simple_process_execute_0_fast_no_reg_no_agg, (funcp)execute_12, (funcp)execute_14, (funcp)execute_31, (funcp)execute_32, (funcp)execute_18, (funcp)execute_19, (funcp)execute_20, (funcp)execute_54, (funcp)execute_55, (funcp)execute_56, (funcp)execute_57, (funcp)execute_58, (funcp)vlog_transfunc_eventcallback};
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const int NumRelocateId= 50;
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||||
void relocate(char *dp)
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{
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iki_relocate(dp, "xsim.dir/tb_exp4_behav/xsim.reloc", (void **)funcTab, 50);
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/*Populate the transaction function pointer field in the whole net structure */
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||||
}
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||||
|
||||
void sensitize(char *dp)
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||||
{
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iki_sensitize(dp, "xsim.dir/tb_exp4_behav/xsim.reloc");
|
||||
}
|
||||
|
||||
void simulate(char *dp)
|
||||
{
|
||||
iki_schedule_processes_at_time_zero(dp, "xsim.dir/tb_exp4_behav/xsim.reloc");
|
||||
// Initialize Verilog nets in mixed simulation, for the cases when the value at time 0 should be propagated from the mixed language Vhdl net
|
||||
iki_execute_processes();
|
||||
|
||||
// Schedule resolution functions for the multiply driven Verilog nets that have strength
|
||||
// Schedule transaction functions for the singly driven Verilog nets that have strength
|
||||
|
||||
}
|
||||
#include "iki_bridge.h"
|
||||
void relocate(char *);
|
||||
|
||||
void sensitize(char *);
|
||||
|
||||
void simulate(char *);
|
||||
|
||||
extern SYSTEMCLIB_IMP_DLLSPEC void local_register_implicit_channel(int, char*);
|
||||
extern void implicit_HDL_SCinstatiate();
|
||||
|
||||
extern int xsim_argc_copy ;
|
||||
extern char** xsim_argv_copy ;
|
||||
|
||||
int main(int argc, char **argv)
|
||||
{
|
||||
iki_heap_initialize("ms", "isimmm", 0, 2147483648) ;
|
||||
iki_set_sv_type_file_path_name("xsim.dir/tb_exp4_behav/xsim.svtype");
|
||||
iki_set_crvs_dump_file_path_name("xsim.dir/tb_exp4_behav/xsim.crvsdump");
|
||||
void* design_handle = iki_create_design("xsim.dir/tb_exp4_behav/xsim.mem", (void *)relocate, (void *)sensitize, (void *)simulate, 0, isimBridge_getWdbWriter(), 0, argc, argv);
|
||||
iki_set_rc_trial_count(100);
|
||||
(void) design_handle;
|
||||
return iki_simulate_design();
|
||||
}
|
||||
Binary file not shown.
BIN
Experiments/Exp4/Exp4.sim/sim_1/behav/xsim/xvlog.pb
Normal file
BIN
Experiments/Exp4/Exp4.sim/sim_1/behav/xsim/xvlog.pb
Normal file
Binary file not shown.
43
Experiments/Exp4/Exp4.srcs/sim_1/new/tb_exp4.v
Normal file
43
Experiments/Exp4/Exp4.srcs/sim_1/new/tb_exp4.v
Normal file
@@ -0,0 +1,43 @@
|
||||
`timescale 1ns / 1ps
|
||||
module tb_exp4;
|
||||
reg clk;
|
||||
reg [31:0] Instr;
|
||||
|
||||
LA32R_CPU uut (.clk(clk), .Instr(Instr));
|
||||
|
||||
wire [31:0] r1_val = uut.u_Datapath.u_Registers.regs[1];
|
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wire [31:0] r2_val = uut.u_Datapath.u_Registers.regs[2];
|
||||
wire [31:0] r3_val = uut.u_Datapath.u_Registers.regs[3];
|
||||
wire [31:0] r4_val = uut.u_Datapath.u_Registers.regs[4];
|
||||
wire [31:0] r5_val = uut.u_Datapath.u_Registers.regs[5];
|
||||
|
||||
initial begin clk = 0; forever #5 clk = ~clk; end
|
||||
|
||||
initial begin
|
||||
$display("----------------- 开始实验四仿真-----------------");
|
||||
|
||||
Instr = {3'b001, 4'b0, 20'h12345, 5'd1}; #10;
|
||||
$display("执行 lu12i.w r1, 0x12345. 期望 r1=12345000. 实际 r1=%h", r1_val);
|
||||
|
||||
Instr = {3'b001, 4'b0, 20'hABCDE, 5'd2}; #10;
|
||||
$display("执行 lu12i.w r2, 0xABCDE. 期望 r2=abcde000. 实际 r2=%h", r2_val);
|
||||
|
||||
Instr = {3'b000, 7'b0, 7'b0000010, 5'd2, 5'd1, 5'd3}; #10;
|
||||
$display("执行 add.w r3, r1, r2. 期望 r3=be023000. 实际 r3=%h", r3_val);
|
||||
|
||||
Instr = {3'b000, 7'b0, 7'b0000100, 5'd2, 5'd1, 5'd4}; #10;
|
||||
$display("执行 slt r4, r1, r2. 期望 r4=00000000. 实际 r4=%h", r4_val);
|
||||
|
||||
Instr = {3'b000, 7'b0, 7'b0000101, 5'd2, 5'd1, 5'd5}; #10;
|
||||
$display("执行 sltu r5, r1, r2. 期望 r5=00000001. 实际 r5=%h", r5_val);
|
||||
|
||||
Instr = {3'b011, 7'b0, 12'd100, 5'd2, 5'd1}; #10;
|
||||
$display("执行 st.w r1, r2, 100. 将r1的值存入内存");
|
||||
|
||||
Instr = {3'b010, 7'b0, 12'd100, 5'd2, 5'd3}; #10;
|
||||
$display("执行 ld.w r3, r2, 100. 期望 r3=12345000. 实际 r3=%h", r3_val);
|
||||
|
||||
$display("\n----------------- 实验四仿真结束 -----------------");
|
||||
$stop;
|
||||
end
|
||||
endmodule
|
||||
187
Experiments/Exp4/Exp4.xpr
Normal file
187
Experiments/Exp4/Exp4.xpr
Normal file
@@ -0,0 +1,187 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<!-- Product Version: Vivado v2018.1 (64-bit) -->
|
||||
<!-- -->
|
||||
<!-- Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. -->
|
||||
|
||||
<Project Version="7" Minor="36" Path="D:/Schoolwork/ComputerComposition/Experiments/Exp4/Exp4.xpr">
|
||||
<DefaultLaunch Dir="$PRUNDIR"/>
|
||||
<Configuration>
|
||||
<Option Name="Id" Val="ae2a6b03df4749b48fa62497cdcfc9a7"/>
|
||||
<Option Name="Part" Val="xc7a35tcsg324-1"/>
|
||||
<Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
|
||||
<Option Name="CompiledLibDirXSim" Val=""/>
|
||||
<Option Name="CompiledLibDirModelSim" Val="$PCACHEDIR/compile_simlib/modelsim"/>
|
||||
<Option Name="CompiledLibDirQuesta" Val="$PCACHEDIR/compile_simlib/questa"/>
|
||||
<Option Name="CompiledLibDirIES" Val="$PCACHEDIR/compile_simlib/ies"/>
|
||||
<Option Name="CompiledLibDirXcelium" Val="$PCACHEDIR/compile_simlib/xcelium"/>
|
||||
<Option Name="CompiledLibDirVCS" Val="$PCACHEDIR/compile_simlib/vcs"/>
|
||||
<Option Name="CompiledLibDirRiviera" Val="$PCACHEDIR/compile_simlib/riviera"/>
|
||||
<Option Name="CompiledLibDirActivehdl" Val="$PCACHEDIR/compile_simlib/activehdl"/>
|
||||
<Option Name="BoardPart" Val=""/>
|
||||
<Option Name="ActiveSimSet" Val="sim_1"/>
|
||||
<Option Name="DefaultLib" Val="xil_defaultlib"/>
|
||||
<Option Name="ProjectType" Val="Default"/>
|
||||
<Option Name="IPOutputRepo" Val="$PCACHEDIR/ip"/>
|
||||
<Option Name="IPCachePermission" Val="read"/>
|
||||
<Option Name="IPCachePermission" Val="write"/>
|
||||
<Option Name="EnableCoreContainer" Val="FALSE"/>
|
||||
<Option Name="CreateRefXciForCoreContainers" Val="FALSE"/>
|
||||
<Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
|
||||
<Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
|
||||
<Option Name="EnableBDX" Val="FALSE"/>
|
||||
<Option Name="DSAVendor" Val="xilinx"/>
|
||||
<Option Name="DSANumComputeUnits" Val="60"/>
|
||||
<Option Name="WTXSimLaunchSim" Val="9"/>
|
||||
<Option Name="WTModelSimLaunchSim" Val="0"/>
|
||||
<Option Name="WTQuestaLaunchSim" Val="0"/>
|
||||
<Option Name="WTIesLaunchSim" Val="0"/>
|
||||
<Option Name="WTVcsLaunchSim" Val="0"/>
|
||||
<Option Name="WTRivieraLaunchSim" Val="0"/>
|
||||
<Option Name="WTActivehdlLaunchSim" Val="0"/>
|
||||
<Option Name="WTXSimExportSim" Val="0"/>
|
||||
<Option Name="WTModelSimExportSim" Val="0"/>
|
||||
<Option Name="WTQuestaExportSim" Val="0"/>
|
||||
<Option Name="WTIesExportSim" Val="0"/>
|
||||
<Option Name="WTVcsExportSim" Val="0"/>
|
||||
<Option Name="WTRivieraExportSim" Val="0"/>
|
||||
<Option Name="WTActivehdlExportSim" Val="0"/>
|
||||
<Option Name="GenerateIPUpgradeLog" Val="TRUE"/>
|
||||
<Option Name="XSimRadix" Val="hex"/>
|
||||
<Option Name="XSimTimeUnit" Val="ns"/>
|
||||
<Option Name="XSimArrayDisplayLimit" Val="1024"/>
|
||||
<Option Name="XSimTraceLimit" Val="65536"/>
|
||||
<Option Name="SimTypes" Val="rtl"/>
|
||||
</Configuration>
|
||||
<FileSets Version="1" Minor="31">
|
||||
<FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1">
|
||||
<Filter Type="Srcs"/>
|
||||
<File Path="$PPRDIR/../Shared/ALU.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../Shared/Controller.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../Shared/DataRAM.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../Shared/Datapath.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../Shared/Ext.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../Shared/Registers.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../Shared/LA32R_CPU.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<Config>
|
||||
<Option Name="DesignMode" Val="RTL"/>
|
||||
<Option Name="TopModule" Val="LA32R_CPU"/>
|
||||
<Option Name="TopAutoSet" Val="TRUE"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1">
|
||||
<Filter Type="Constrs"/>
|
||||
<Config>
|
||||
<Option Name="ConstrsType" Val="XDC"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1">
|
||||
<File Path="$PSRCDIR/sim_1/new/tb_exp4.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<Config>
|
||||
<Option Name="DesignMode" Val="RTL"/>
|
||||
<Option Name="TopModule" Val="tb_exp4"/>
|
||||
<Option Name="TopLib" Val="xil_defaultlib"/>
|
||||
<Option Name="TopAutoSet" Val="TRUE"/>
|
||||
<Option Name="TransportPathDelay" Val="0"/>
|
||||
<Option Name="TransportIntDelay" Val="0"/>
|
||||
<Option Name="SrcSet" Val="sources_1"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
</FileSets>
|
||||
<Simulators>
|
||||
<Simulator Name="XSim">
|
||||
<Option Name="Description" Val="Vivado Simulator"/>
|
||||
<Option Name="CompiledLib" Val="0"/>
|
||||
</Simulator>
|
||||
<Simulator Name="ModelSim">
|
||||
<Option Name="Description" Val="ModelSim Simulator"/>
|
||||
</Simulator>
|
||||
<Simulator Name="Questa">
|
||||
<Option Name="Description" Val="Questa Advanced Simulator"/>
|
||||
</Simulator>
|
||||
<Simulator Name="Riviera">
|
||||
<Option Name="Description" Val="Riviera-PRO Simulator"/>
|
||||
</Simulator>
|
||||
<Simulator Name="ActiveHDL">
|
||||
<Option Name="Description" Val="Active-HDL Simulator"/>
|
||||
</Simulator>
|
||||
</Simulators>
|
||||
<Runs Version="1" Minor="10">
|
||||
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7a35tcsg324-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2018">
|
||||
<Desc>Vivado Synthesis Defaults</Desc>
|
||||
</StratHandle>
|
||||
<Step Id="synth_design"/>
|
||||
</Strategy>
|
||||
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2018"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
</Run>
|
||||
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7a35tcsg324-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2018">
|
||||
<Desc>Default settings for Implementation.</Desc>
|
||||
</StratHandle>
|
||||
<Step Id="init_design"/>
|
||||
<Step Id="opt_design"/>
|
||||
<Step Id="power_opt_design"/>
|
||||
<Step Id="place_design"/>
|
||||
<Step Id="post_place_power_opt_design"/>
|
||||
<Step Id="phys_opt_design"/>
|
||||
<Step Id="route_design"/>
|
||||
<Step Id="post_route_phys_opt_design"/>
|
||||
<Step Id="write_bitstream"/>
|
||||
</Strategy>
|
||||
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2018"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
</Run>
|
||||
</Runs>
|
||||
<Board/>
|
||||
</Project>
|
||||
Reference in New Issue
Block a user