Initial commit

Experiments/Exp4/Exp4.srcs/sim_1/new/tb_exp4.v

@@ -0,0 +1,43 @@
+`timescale 1ns / 1ps
+module tb_exp4;
+    reg clk;
+    reg [31:0] Instr;
+
+    LA32R_CPU uut (.clk(clk), .Instr(Instr));
+    
+    wire [31:0] r1_val = uut.u_Datapath.u_Registers.regs[1];
+    wire [31:0] r2_val = uut.u_Datapath.u_Registers.regs[2];
+    wire [31:0] r3_val = uut.u_Datapath.u_Registers.regs[3];
+    wire [31:0] r4_val = uut.u_Datapath.u_Registers.regs[4];
+    wire [31:0] r5_val = uut.u_Datapath.u_Registers.regs[5];
+
+    initial begin clk = 0; forever #5 clk = ~clk; end
+
+    initial begin
+        $display("----------------- 开始实验四仿真-----------------");
+        
+        Instr = {3'b001, 4'b0, 20'h12345, 5'd1}; #10;
+        $display("执行 lu12i.w r1, 0x12345. 期望 r1=12345000. 实际 r1=%h", r1_val);
+        
+        Instr = {3'b001, 4'b0, 20'hABCDE, 5'd2}; #10;
+        $display("执行 lu12i.w r2, 0xABCDE. 期望 r2=abcde000. 实际 r2=%h", r2_val);
+        
+        Instr = {3'b000, 7'b0, 7'b0000010, 5'd2, 5'd1, 5'd3}; #10;
+        $display("执行 add.w r3, r1, r2. 期望 r3=be023000. 实际 r3=%h", r3_val);
+        
+        Instr = {3'b000, 7'b0, 7'b0000100, 5'd2, 5'd1, 5'd4}; #10;
+        $display("执行 slt r4, r1, r2. 期望 r4=00000000. 实际 r4=%h", r4_val);
+        
+        Instr = {3'b000, 7'b0, 7'b0000101, 5'd2, 5'd1, 5'd5}; #10;
+        $display("执行 sltu r5, r1, r2. 期望 r5=00000001. 实际 r5=%h", r5_val);
+        
+        Instr = {3'b011, 7'b0, 12'd100, 5'd2, 5'd1}; #10;
+        $display("执行 st.w r1, r2, 100. 将r1的值存入内存");
+        
+        Instr = {3'b010, 7'b0, 12'd100, 5'd2, 5'd3}; #10;
+        $display("执行 ld.w r3, r2, 100. 期望 r3=12345000. 实际 r3=%h", r3_val);
+        
+        $display("\n----------------- 实验四仿真结束 -----------------");
+        $stop;
+    end
+endmodule