Initial commit

Experiments/Shared/DR.v

@@ -0,0 +1,12 @@
+module DR(
+    input         clk,
+    input         WE,
+    input  [31:0] DataIn,
+    output reg [31:0] DataOut
+);
+    always @(posedge clk) begin
+        if (WE) begin
+            DataOut <= DataIn;
+        end
+    end
+endmodule