Initial commit

2025-11-06 09:35:54 +08:00
commit 07678f510c
93 changed files with 3443 additions and 0 deletions
--- a/Experiments/Shared/LA32R_CPU.v
+++ b/Experiments/Shared/LA32R_CPU.v
@@ -0,0 +1,14 @@
+module LA32R_CPU(
+    input clk,
+    input [31:0] Instr
+);
+    wire RegWr, MemToReg, MemWrEn, ALUBSrc, srcReg;
+    wire [1:0] ExtOp;
+    wire [2:0] AluCtrl;
+    wire Zero;
+
+    Controller u_Controller(.Opcode_in(Instr[31:15]), .RegWr(RegWr), .MemToReg(MemToReg), .MemWrEn(MemWrEn),
+        .ALUBSrc(ALUBSrc), .srcReg(srcReg), .ExtOp(ExtOp), .AluCtrl(AluCtrl));
+    Datapath u_Datapath(.clk(clk), .Instr(Instr), .RegWr(RegWr), .MemToReg(MemToReg), .MemWrEn(MemWrEn),
+        .ALUBSrc(ALUBSrc), .srcReg(srcReg), .ExtOp(ExtOp), .AluCtrl(AluCtrl), .Zero(Zero));
+endmodule