12 lines
229 B
Verilog
12 lines
229 B
Verilog
module DR(
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input clk,
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input WE,
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input [31:0] DataIn,
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output reg [31:0] DataOut
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);
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always @(posedge clk) begin
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if (WE) begin
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DataOut <= DataIn;
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end
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end
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endmodule |