42 lines
1.0 KiB
Verilog
42 lines
1.0 KiB
Verilog
`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Engineer:
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//
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// Create Date: 2025/05/30 20:49:51
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// Design Name:
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// Module Name: Registers
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// Project Name:
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// Target Devices:
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// Tool Versions:
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// Description:
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//
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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//////////////////////////////////////////////////////////////////////////////////
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module Registers (
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input wire clk,
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input wire RegWr,
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input wire [4:0] Ra,
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input wire [4:0] Rb,
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input wire [4:0] Rw,
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input wire [31:0] busW,
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output wire [31:0] busA,
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output wire [31:0] busB
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);
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reg [31:0] register_file [31:0];
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always @(posedge clk) begin
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if (RegWr && (Rw != 5'b00000)) begin
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register_file[Rw] <= busW;
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end
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end
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assign busA = (Ra == 5'b00000) ? 32'h00000000 : register_file[Ra];
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assign busB = (Rb == 5'b00000) ? 32'h00000000 : register_file[Rb];
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endmodule
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