31 lines
890 B
Verilog
31 lines
890 B
Verilog
module ALU(
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input [31:0] a,
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input [31:0] b,
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input [2:0] AluCtrl,
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output reg [31:0] AddResult,
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output reg Zero
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);
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parameter ADD = 3'b000;
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parameter SUB = 3'b001;
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parameter AND = 3'b010;
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parameter OR = 3'b011;
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parameter NOR = 3'b100;
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parameter SLT = 3'b101;
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parameter SLTU = 3'b110;
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parameter PASSB= 3'b111;
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always @(*) begin
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case (AluCtrl)
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ADD: AddResult = a + b;
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SUB: AddResult = a - b;
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AND: AddResult = a & b;
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OR: AddResult = a | b;
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NOR: AddResult = ~(a | b);
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SLT: AddResult = ($signed(a) < $signed(b)) ? 32'd1 : 32'd0;
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SLTU: AddResult = (a < b) ? 32'd1 : 32'd0;
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PASSB:AddResult = b;
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default: AddResult = 32'hxxxxxxxx;
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endcase
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Zero = (AddResult == 32'd0);
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end
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endmodule |