24 lines
1.0 KiB
Verilog
24 lines
1.0 KiB
Verilog
module Datapath(
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input clk,
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input [31:0] Instr,
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input RegWr,
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input MemToReg,
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input MemWrEn,
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input ALUBSrc,
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input srcReg,
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input [1:0] ExtOp,
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input [2:0] AluCtrl,
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output Zero
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);
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wire [31:0] busA_out, busB_out, ext_out, alu_in_b, alu_result, ram_data_out, reg_write_data;
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wire [4:0] rj = Instr[9:5];
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wire [4:0] rk_or_rd_store = Instr[14:10];
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wire [4:0] rd_write = Instr[4:0];
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Registers u_Registers(.clk(clk), .RegWr(RegWr), .Ra(rj), .Rb(srcReg ? Instr[4:0] : rk_or_rd_store), .Rw(rd_write), .busW(reg_write_data), .busA(busA_out), .busB(busB_out));
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Ext u_Ext(.DataIn(Instr), .ExtOp(ExtOp), .DataOut(ext_out));
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assign alu_in_b = ALUBSrc ? ext_out : busB_out;
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ALU u_ALU(.a(busA_out), .b(alu_in_b), .AluCtrl(AluCtrl), .AddResult(alu_result), .Zero(Zero));
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DataRAM u_DataRAM(.clk(clk), .MemWrEn(MemWrEn), .addr(alu_result), .data_in(busB_out), .data_out(ram_data_out));
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assign reg_write_data = MemToReg ? ram_data_out : alu_result;
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endmodule |