23 lines
718 B
Verilog
23 lines
718 B
Verilog
module Ext(
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input [31:0] DataIn,
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input [1:0] ExtOp,
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output [31:0] DataOut
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);
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wire [31:0] imm12, imm16, imm20, imm26;
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assign imm12 = {{20{DataIn[21]}}, DataIn[21:10]};
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assign imm16 = {{14{DataIn[25]}}, DataIn[25:10], 2'b0};
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assign imm20 = {DataIn[24:5], 12'b0};
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assign imm26 = {{4{DataIn[9]}}, DataIn[9:0], DataIn[25:10], 2'b0};
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reg [31:0] temp_DataOut;
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always @(*) begin
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case (ExtOp)
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2'b00: temp_DataOut = imm12;
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2'b01: temp_DataOut = imm16;
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2'b10: temp_DataOut = imm20;
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2'b11: temp_DataOut = imm26;
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default: temp_DataOut = 32'hxxxxxxxx;
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endcase
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end
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assign DataOut = temp_DataOut;
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endmodule |