14 lines
567 B
Verilog
14 lines
567 B
Verilog
module LA32R_CPU(
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input clk,
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input [31:0] Instr
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);
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wire RegWr, MemToReg, MemWrEn, ALUBSrc, srcReg;
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wire [1:0] ExtOp;
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wire [2:0] AluCtrl;
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wire Zero;
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Controller u_Controller(.Opcode_in(Instr[31:15]), .RegWr(RegWr), .MemToReg(MemToReg), .MemWrEn(MemWrEn),
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.ALUBSrc(ALUBSrc), .srcReg(srcReg), .ExtOp(ExtOp), .AluCtrl(AluCtrl));
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Datapath u_Datapath(.clk(clk), .Instr(Instr), .RegWr(RegWr), .MemToReg(MemToReg), .MemWrEn(MemWrEn),
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.ALUBSrc(ALUBSrc), .srcReg(srcReg), .ExtOp(ExtOp), .AluCtrl(AluCtrl), .Zero(Zero));
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endmodule |