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2025-11-06 10:08:01 +08:00
commit 0bded5b86e
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16
Ch8421_Yv3/Ch8421_Yv3.srcs/constrs_1/new/Ch8421_Yv3.xdc Normal file
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set_property IOSTANDARD LVCMOS33 [get_ports {Bin[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {Bin[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {Bin[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {Bin[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {Yout[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {Yout[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {Yout[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {Yout[0]}]
set_property PACKAGE_PIN P5 [get_ports {Bin[3]}]
set_property PACKAGE_PIN P4 [get_ports {Bin[2]}]
set_property PACKAGE_PIN P3 [get_ports {Bin[1]}]
set_property PACKAGE_PIN P2 [get_ports {Bin[0]}]
set_property PACKAGE_PIN F6 [get_ports {Yout[3]}]
set_property PACKAGE_PIN G4 [get_ports {Yout[2]}]
set_property PACKAGE_PIN G3 [get_ports {Yout[1]}]
set_property PACKAGE_PIN J4 [get_ports {Yout[0]}]

46
Ch8421_Yv3/Ch8421_Yv3.srcs/sim_1/new/Ch8421_Yv3_sim.v Normal file
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`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2024/10/10 10:17:39
// Design Name:
// Module Name: Ch8421_Yv3_sim
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Ch8421_Yv3_sim();
reg [3:0] Bin;
wire [3:0] Yout;
Ch8421_Yv3 U1(.Bin(Bin), .Yout(Yout));
initial begin
Bin <= 4'b0000;#100;
Bin <= 4'b0001;#100;
Bin <= 4'b0010;#100;
Bin <= 4'b0011;#100;
Bin <= 4'b0100;#100;
Bin <= 4'b0101;#100;
Bin <= 4'b0110;#100;
Bin <= 4'b0111;#100;
Bin <= 4'b1000;#100;
Bin <= 4'b1001;#100;
Bin <= 4'b1010;#100;
Bin <= 4'b1011;#100;
Bin <= 4'b1100;#100;
Bin <= 4'b1101;#100;
Bin <= 4'b1110;#100;
Bin <= 4'b1111;#100;
$stop;
end
endmodule

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Ch8421_Yv3/Ch8421_Yv3.srcs/sources_1/new/Ch8421_Yv3.v Normal file
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`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2024/10/10 10:12:57
// Design Name:
// Module Name: Ch8421_Yv3
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Ch8421_Yv3(Bin, Yout);
input [3:0] Bin;
output [3:0] Yout;
reg [3:0] Yout;
always @ (Bin)
if (Bin <= 4'b1001)
Yout = Bin + 4'b0011;
else Yout = 0;
endmodule