Initial commit

Exp1-1/Exp1-1.srcs/constrs_1/new/EX1.xdc

@@ -0,0 +1,10 @@
+set_property PACKAGE_PIN J3 [get_ports {z[2]}]
+set_property PACKAGE_PIN J2 [get_ports {z[1]}]
+set_property PACKAGE_PIN K2 [get_ports {z[0]}]
+set_property PACKAGE_PIN P5 [get_ports a]
+set_property PACKAGE_PIN P4 [get_ports b]
+set_property IOSTANDARD LVCMOS33 [get_ports {z[2]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {z[1]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {z[0]}]
+set_property IOSTANDARD LVCMOS33 [get_ports b]
+set_property IOSTANDARD LVCMOS33 [get_ports a]

Exp1-1/Exp1-1.srcs/sim_1/new/sim4First.v

@@ -0,0 +1,34 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date: 2024/09/23 23:58:54
+// Design Name: 
+// Module Name: sim4First
+// Project Name: 
+// Target Devices: 
+// Tool Versions: 
+// Description: 
+// 
+// Dependencies: 
+// 
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+// 
+//////////////////////////////////////////////////////////////////////////////////
+
+
+module sim4First( );
+reg a;
+reg b;
+wire [2:0] z;
+First uut( .a(a), .b(b), .z(z) );
+always begin
+a = 0; b = 0; #100;
+a = 0; b = 1; #100;
+a = 1; b = 0; #100;
+a = 1; b = 1; #100;
+end
+endmodule

Exp1-1/Exp1-1.srcs/sources_1/new/First.v

@@ -0,0 +1,30 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date: 2024/09/23 23:52:50
+// Design Name: 
+// Module Name: First
+// Project Name: 
+// Target Devices: 
+// Tool Versions: 
+// Description: 
+// 
+// Dependencies: 
+// 
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+// 
+//////////////////////////////////////////////////////////////////////////////////
+
+
+module First(a,b,z);
+input a,b;
+output z;
+wire [2:0] z;
+assign z[0] = a&b;
+assign z[1] = a|b;
+assign z[2] = a^b;
+endmodule