Initial commit

Exp1-2-2/Exp1-2-2.srcs/constrs_1/new/mux41.xdc

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+set_property PACKAGE_PIN P5 [get_ports {I[0]}]
+set_property PACKAGE_PIN P4 [get_ports {I[1]}]
+set_property PACKAGE_PIN P3 [get_ports {I[2]}]
+set_property PACKAGE_PIN P2 [get_ports {I[3]}]
+set_property PACKAGE_PIN R2 [get_ports {S[1]}]
+set_property PACKAGE_PIN M4 [get_ports {S[0]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {I[3]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {I[2]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {I[1]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {I[0]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {S[1]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {S[0]}]
+set_property PACKAGE_PIN F6 [get_ports Y]
+set_property IOSTANDARD LVCMOS33 [get_ports Y]

Exp1-2-2/Exp1-2-2.srcs/sim_1/new/sim4mux41.v

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+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date: 2024/09/25 20:35:36
+// Design Name: 
+// Module Name: sim4mux41
+// Project Name: 
+// Target Devices: 
+// Tool Versions: 
+// Description: 
+// 
+// Dependencies: 
+// 
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+// 
+//////////////////////////////////////////////////////////////////////////////////
+
+
+module sim4mux41();
+reg [3:0] I;
+reg [1:0] S;
+wire Y;
+integer i, s;
+mux41 uut (.I(I), .S(S), .Y(Y));
+initial begin
+    for (i = 0; i < 16; i = i + 1) begin
+        for (s = 0; s < 4; s = s + 1) begin
+            I = i;
+            S = s;
+            #10;
+        end
+    end
+end
+endmodule

Exp1-2-2/Exp1-2-2.srcs/sim_1/new/sim4mux41_alt.v

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+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date: 2024/09/26 11:52:05
+// Design Name: 
+// Module Name: sim4mux41_alt
+// Project Name: 
+// Target Devices: 
+// Tool Versions: 
+// Description: 
+// 
+// Dependencies: 
+// 
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+// 
+//////////////////////////////////////////////////////////////////////////////////
+
+
+module sim4mux41_alt();
+reg [3:0] I;
+reg [1:0] S;
+wire Y;
+mux41_alt test_alt (.I(I), .S(S), .Y(Y));
+initial begin
+    I = 4'b0000; S=2'b00; //initialize
+    I = 4'b0001; S=2'b00; #100; // A
+    I = 4'b0010; S=2'b01; #100; // B
+    I = 4'b0100; S=2'b10; #100; // C
+    I = 4'b1000; S=2'b11; #100; // D
+end
+endmodule

Exp1-2-2/Exp1-2-2.srcs/sources_1/new/mux21.v

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+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date: 2024/09/24 15:51:41
+// Design Name: 
+// Module Name: mux21
+// Project Name: 
+// Target Devices: 
+// Tool Versions: 
+// Description: 
+// 
+// Dependencies: 
+// 
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+// 
+//////////////////////////////////////////////////////////////////////////////////
+
+
+module mux21( input a,input b,input c,output y);
+assign y = c ? b : a;
+endmodule

Exp1-2-2/Exp1-2-2.srcs/sources_1/new/mux41.v

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+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date: 2024/09/24 15:50:25
+// Design Name: 
+// Module Name: mux41
+// Project Name: 
+// Target Devices: 
+// Tool Versions: 
+// Description: 
+// 
+// Dependencies: 
+// 
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+// 
+//////////////////////////////////////////////////////////////////////////////////
+
+
+module mux41(input [3:0] I, input [1:0] S, output Y );
+wire m,n;
+mux21 M1(.a(I[0]) , .b(I[1]) , .c(S[0]) , .y(m) );
+mux21 M2(.a(I[2]) , .b(I[3]) , .c(S[0]) , .y(n) );
+mux21 M3(.a(m) , .b(n) , .c(S[1]) , .y(Y) );
+endmodule

Exp1-2-2/Exp1-2-2.srcs/sources_1/new/mux41_alt.v

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+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date: 2024/09/26 11:43:00
+// Design Name: 
+// Module Name: mux41_alt
+// Project Name: 
+// Target Devices: 
+// Tool Versions: 
+// Description: 
+// 
+// Dependencies: 
+// 
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+// 
+//////////////////////////////////////////////////////////////////////////////////
+
+
+module mux41_alt(I,S,Y);
+input [3:0] I;
+input [1:0] S;
+output Y;
+reg Y;
+always begin
+    case (S)
+        2'b00: Y = I[4'b0001];
+        2'b01: Y = I[4'b0010];
+        2'b10: Y = I[4'b0100];
+        2'b11: Y = I[4'b1000];
+        default: Y = 0;
+    endcase
+end
+endmodule