Initial commit

Exp1-2-2/Exp1-2-2.srcs/sim_1/new/sim4mux41.v

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+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date: 2024/09/25 20:35:36
+// Design Name: 
+// Module Name: sim4mux41
+// Project Name: 
+// Target Devices: 
+// Tool Versions: 
+// Description: 
+// 
+// Dependencies: 
+// 
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+// 
+//////////////////////////////////////////////////////////////////////////////////
+
+
+module sim4mux41();
+reg [3:0] I;
+reg [1:0] S;
+wire Y;
+integer i, s;
+mux41 uut (.I(I), .S(S), .Y(Y));
+initial begin
+    for (i = 0; i < 16; i = i + 1) begin
+        for (s = 0; s < 4; s = s + 1) begin
+            I = i;
+            S = s;
+            #10;
+        end
+    end
+end
+endmodule

Exp1-2-2/Exp1-2-2.srcs/sim_1/new/sim4mux41_alt.v

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+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date: 2024/09/26 11:52:05
+// Design Name: 
+// Module Name: sim4mux41_alt
+// Project Name: 
+// Target Devices: 
+// Tool Versions: 
+// Description: 
+// 
+// Dependencies: 
+// 
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+// 
+//////////////////////////////////////////////////////////////////////////////////
+
+
+module sim4mux41_alt();
+reg [3:0] I;
+reg [1:0] S;
+wire Y;
+mux41_alt test_alt (.I(I), .S(S), .Y(Y));
+initial begin
+    I = 4'b0000; S=2'b00; //initialize
+    I = 4'b0001; S=2'b00; #100; // A
+    I = 4'b0010; S=2'b01; #100; // B
+    I = 4'b0100; S=2'b10; #100; // C
+    I = 4'b1000; S=2'b11; #100; // D
+end
+endmodule