Initial commit

Exp1-2-2/Exp1-2-2.srcs/sources_1/new/mux21.v

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+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date: 2024/09/24 15:51:41
+// Design Name: 
+// Module Name: mux21
+// Project Name: 
+// Target Devices: 
+// Tool Versions: 
+// Description: 
+// 
+// Dependencies: 
+// 
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+// 
+//////////////////////////////////////////////////////////////////////////////////
+
+
+module mux21( input a,input b,input c,output y);
+assign y = c ? b : a;
+endmodule

Exp1-2-2/Exp1-2-2.srcs/sources_1/new/mux41.v

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+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date: 2024/09/24 15:50:25
+// Design Name: 
+// Module Name: mux41
+// Project Name: 
+// Target Devices: 
+// Tool Versions: 
+// Description: 
+// 
+// Dependencies: 
+// 
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+// 
+//////////////////////////////////////////////////////////////////////////////////
+
+
+module mux41(input [3:0] I, input [1:0] S, output Y );
+wire m,n;
+mux21 M1(.a(I[0]) , .b(I[1]) , .c(S[0]) , .y(m) );
+mux21 M2(.a(I[2]) , .b(I[3]) , .c(S[0]) , .y(n) );
+mux21 M3(.a(m) , .b(n) , .c(S[1]) , .y(Y) );
+endmodule

Exp1-2-2/Exp1-2-2.srcs/sources_1/new/mux41_alt.v

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+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date: 2024/09/26 11:43:00
+// Design Name: 
+// Module Name: mux41_alt
+// Project Name: 
+// Target Devices: 
+// Tool Versions: 
+// Description: 
+// 
+// Dependencies: 
+// 
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+// 
+//////////////////////////////////////////////////////////////////////////////////
+
+
+module mux41_alt(I,S,Y);
+input [3:0] I;
+input [1:0] S;
+output Y;
+reg Y;
+always begin
+    case (S)
+        2'b00: Y = I[4'b0001];
+        2'b01: Y = I[4'b0010];
+        2'b10: Y = I[4'b0100];
+        2'b11: Y = I[4'b1000];
+        default: Y = 0;
+    endcase
+end
+endmodule