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Exp1-2-3/Exp1-2-3.srcs/sim_1/new/LU_sim.v
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Exp1-2-3/Exp1-2-3.srcs/sim_1/new/LU_sim.v
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`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Engineer:
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//
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// Create Date: 2024/09/26 10:31:31
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// Design Name:
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// Module Name: LU_sim
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// Project Name:
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// Target Devices:
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// Tool Versions:
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// Description:
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//
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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//////////////////////////////////////////////////////////////////////////////////
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module sim_LU();
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reg a,b;
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reg [1:0]s;
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LU u3(.a(a),.b(b),.s(s),.Y(Y));
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initial begin
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a=0;b=0;s=2'b00;#50;
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a=0;b=0;s=2'b01;#50;
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a=0;b=0;s=2'b10;#50;
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a=0;b=0;s=2'b11;#50;
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a=0;b=1;s=2'b00;#50;
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a=0;b=1;s=2'b01;#50;
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a=0;b=1;s=2'b10;#50;
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a=0;b=1;s=2'b11;#50;
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a=1;b=0;s=2'b00;#50;
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a=1;b=0;s=2'b01;#50;
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a=1;b=0;s=2'b10;#50;
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a=1;b=0;s=2'b11;#50;
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a=1;b=1;s=2'b00;#50;
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a=1;b=1;s=2'b01;#50;
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a=1;b=1;s=2'b10;#50;
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a=1;b=1;s=2'b11;#50;
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end
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endmodule
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