Initial commit

Exp2/Exp2.srcs/constrs_1/new/VotingMachine.xdc

@@ -0,0 +1,56 @@
+set_property IOSTANDARD LVCMOS33 [get_ports {seg1[6]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {seg1[5]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {seg1[4]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {seg1[3]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {seg1[2]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {seg1[1]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {seg1[0]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {seg2[6]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {seg2[5]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {seg2[4]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {seg2[3]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {seg2[2]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {seg2[1]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {seg2[0]}]
+set_property PACKAGE_PIN B4 [get_ports {seg1[6]}]
+set_property PACKAGE_PIN A4 [get_ports {seg1[5]}]
+set_property PACKAGE_PIN A3 [get_ports {seg1[4]}]
+set_property PACKAGE_PIN B1 [get_ports {seg1[3]}]
+set_property PACKAGE_PIN A1 [get_ports {seg1[2]}]
+set_property PACKAGE_PIN B3 [get_ports {seg1[1]}]
+set_property PACKAGE_PIN B2 [get_ports {seg1[0]}]
+set_property PACKAGE_PIN D4 [get_ports {seg2[6]}]
+set_property PACKAGE_PIN E3 [get_ports {seg2[5]}]
+set_property PACKAGE_PIN D3 [get_ports {seg2[4]}]
+set_property PACKAGE_PIN F4 [get_ports {seg2[3]}]
+set_property PACKAGE_PIN F3 [get_ports {seg2[2]}]
+set_property PACKAGE_PIN E2 [get_ports {seg2[1]}]
+set_property PACKAGE_PIN D2 [get_ports {seg2[0]}]
+
+set_property IOSTANDARD LVCMOS33 [get_ports {seg_cs1[3]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {seg_cs1[2]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {seg_cs1[1]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {seg_cs1[0]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {seg_cs2[3]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {seg_cs2[2]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {seg_cs2[1]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {seg_cs2[0]}]
+set_property PACKAGE_PIN G2 [get_ports {seg_cs1[3]}]
+set_property PACKAGE_PIN C2 [get_ports {seg_cs1[2]}]
+set_property PACKAGE_PIN C1 [get_ports {seg_cs1[1]}]
+set_property PACKAGE_PIN H1 [get_ports {seg_cs1[0]}]
+set_property PACKAGE_PIN G1 [get_ports {seg_cs2[3]}]
+set_property PACKAGE_PIN F1 [get_ports {seg_cs2[2]}]
+set_property PACKAGE_PIN E1 [get_ports {seg_cs2[1]}]
+set_property PACKAGE_PIN G6 [get_ports {seg_cs2[0]}]
+
+set_property IOSTANDARD LVCMOS33 [get_ports {votes[4]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {votes[3]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {votes[2]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {votes[1]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {votes[0]}]
+set_property PACKAGE_PIN P5 [get_ports {votes[4]}]
+set_property PACKAGE_PIN P4 [get_ports {votes[3]}]
+set_property PACKAGE_PIN P3 [get_ports {votes[2]}]
+set_property PACKAGE_PIN P2 [get_ports {votes[1]}]
+set_property PACKAGE_PIN R2 [get_ports {votes[0]}]

Exp2/Exp2.srcs/sim_1/new/tb_VotingMachine.v

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+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date: 2024/10/24 10:08:30
+// Design Name: 
+// Module Name: tb_VotingMachine
+// Project Name: 
+// Target Devices: 
+// Tool Versions: 
+// Description: 
+// 
+// Dependencies: 
+// 
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+// 
+//////////////////////////////////////////////////////////////////////////////////
+
+
+module tb_VotingMachine();
+    reg [4:0] votes;
+    wire [6:0] seg1;
+    wire [6:0] seg2;
+    VotingMachine dut (
+        .votes(votes),
+        .seg1(seg1),
+        .seg2(seg2)
+    );
+    initial begin
+        votes = 5'b00000; #10;
+        votes = 5'b10000; #10;
+        votes = 5'b11000; #10;
+        votes = 5'b11100; #10;
+        votes = 5'b11110; #10;
+        votes = 5'b11111; #10;
+        $stop;
+    end
+endmodule

Exp2/Exp2.srcs/sources_1/new/CoreModule.v

@@ -0,0 +1,35 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date: 2024/10/18 21:46:41
+// Design Name: 
+// Module Name: CoreModule
+// Project Name: 
+// Target Devices: 
+// Tool Versions: 
+// Description: 
+// 
+// Dependencies: 
+// 
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+// 
+//////////////////////////////////////////////////////////////////////////////////
+
+
+module CoreModule(
+    input wire [4:0] votes,
+    output reg [2:0] count,
+    output reg pass
+);
+integer i;
+always @(*) begin
+    count = 0;
+    for (i = 0; i < 5; i = i + 1)
+        count = count + votes[i];
+    pass = (count >= 3);
+end
+endmodule

Exp2/Exp2.srcs/sources_1/new/SegDisplayCtrl.v

@@ -0,0 +1,44 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date: 2024/10/18 21:48:13
+// Design Name: 
+// Module Name: SegDisplayCtrl
+// Project Name: 
+// Target Devices: 
+// Tool Versions: 
+// Description: 
+// 
+// Dependencies: 
+// 
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+// 
+//////////////////////////////////////////////////////////////////////////////////
+
+
+module SegDisplayCtrl(
+    input wire [2:0] count,
+    input wire pass,
+    output reg [6:0] seg1,
+    output reg [6:0] seg2
+);
+always @(*) begin
+    case (count)
+        3'b000: seg1 = 7'b1111110;  // 0
+        3'b001: seg1 = 7'b0110000;  // 1
+        3'b010: seg1 = 7'b1101101;  // 2
+        3'b011: seg1 = 7'b1111001;  // 3
+        3'b100: seg1 = 7'b0110011;  // 4
+        3'b101: seg1 = 7'b1011011;  // 5
+        default: seg1 = 7'b0000000;
+    endcase
+    if (pass)
+        seg2 = 7'b1100111;  // P
+    else
+        seg2 = 7'b1000111;  // F
+end
+endmodule

Exp2/Exp2.srcs/sources_1/new/VotingMachine.v

@@ -0,0 +1,47 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date: 2024/10/18 21:44:02
+// Design Name: 
+// Module Name: VotingMachine
+// Project Name: 
+// Target Devices: 
+// Tool Versions: 
+// Description: 
+// 
+// Dependencies: 
+// 
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+// 
+//////////////////////////////////////////////////////////////////////////////////
+
+
+module VotingMachine(
+    input wire [4:0] votes,
+    output wire [6:0] seg1,
+    output wire [6:0] seg2,
+    output reg [3:0] seg_cs1,
+    output reg [3:0] seg_cs2
+);
+    wire [2:0] count;
+    wire pass;
+CoreModule u1 (
+    .votes(votes),
+    .count(count),
+    .pass(pass)
+);
+SegDisplayCtrl u2 (
+    .count(count),
+    .pass(pass),
+    .seg1(seg1),
+    .seg2(seg2)
+);
+always @(*) begin
+    seg_cs1 = 4'b0001;
+    seg_cs2 = 4'b0001;
+end
+endmodule