Initial commit

Exp2/Exp2.srcs/sources_1/new/CoreModule.v

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+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date: 2024/10/18 21:46:41
+// Design Name: 
+// Module Name: CoreModule
+// Project Name: 
+// Target Devices: 
+// Tool Versions: 
+// Description: 
+// 
+// Dependencies: 
+// 
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+// 
+//////////////////////////////////////////////////////////////////////////////////
+
+
+module CoreModule(
+    input wire [4:0] votes,
+    output reg [2:0] count,
+    output reg pass
+);
+integer i;
+always @(*) begin
+    count = 0;
+    for (i = 0; i < 5; i = i + 1)
+        count = count + votes[i];
+    pass = (count >= 3);
+end
+endmodule

Exp2/Exp2.srcs/sources_1/new/SegDisplayCtrl.v

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+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date: 2024/10/18 21:48:13
+// Design Name: 
+// Module Name: SegDisplayCtrl
+// Project Name: 
+// Target Devices: 
+// Tool Versions: 
+// Description: 
+// 
+// Dependencies: 
+// 
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+// 
+//////////////////////////////////////////////////////////////////////////////////
+
+
+module SegDisplayCtrl(
+    input wire [2:0] count,
+    input wire pass,
+    output reg [6:0] seg1,
+    output reg [6:0] seg2
+);
+always @(*) begin
+    case (count)
+        3'b000: seg1 = 7'b1111110;  // 0
+        3'b001: seg1 = 7'b0110000;  // 1
+        3'b010: seg1 = 7'b1101101;  // 2
+        3'b011: seg1 = 7'b1111001;  // 3
+        3'b100: seg1 = 7'b0110011;  // 4
+        3'b101: seg1 = 7'b1011011;  // 5
+        default: seg1 = 7'b0000000;
+    endcase
+    if (pass)
+        seg2 = 7'b1100111;  // P
+    else
+        seg2 = 7'b1000111;  // F
+end
+endmodule

Exp2/Exp2.srcs/sources_1/new/VotingMachine.v

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+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date: 2024/10/18 21:44:02
+// Design Name: 
+// Module Name: VotingMachine
+// Project Name: 
+// Target Devices: 
+// Tool Versions: 
+// Description: 
+// 
+// Dependencies: 
+// 
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+// 
+//////////////////////////////////////////////////////////////////////////////////
+
+
+module VotingMachine(
+    input wire [4:0] votes,
+    output wire [6:0] seg1,
+    output wire [6:0] seg2,
+    output reg [3:0] seg_cs1,
+    output reg [3:0] seg_cs2
+);
+    wire [2:0] count;
+    wire pass;
+CoreModule u1 (
+    .votes(votes),
+    .count(count),
+    .pass(pass)
+);
+SegDisplayCtrl u2 (
+    .count(count),
+    .pass(pass),
+    .seg1(seg1),
+    .seg2(seg2)
+);
+always @(*) begin
+    seg_cs1 = 4'b0001;
+    seg_cs2 = 4'b0001;
+end
+endmodule