Initial commit

Exp3-1/Exp3-1.srcs/sources_1/new/encoder.v

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+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date: 2024/10/24 10:37:58
+// Design Name: 
+// Module Name: encoder
+// Project Name: 
+// Target Devices: 
+// Tool Versions: 
+// Description: 
+// 
+// Dependencies: 
+// 
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+// 
+//////////////////////////////////////////////////////////////////////////////////
+
+
+module encoder(
+    input en,
+    input [7:0] i,
+    output reg [7:0] i_sig,
+    output wire [6:0] seg1,
+    output wire [7:0] seg2,
+    output reg [3:0] seg_cs1,
+    output reg [3:0] seg_cs2
+    );
+reg out;
+reg [2:0] Y;
+always @(*) begin
+    out = 1;
+    if (en == 0)
+        out = 0;
+    else begin
+        case (i)
+            8'b11111110: begin Y = 3'b000; i_sig = 8'b00000001; end
+            8'b11111101: begin Y = 3'b001; i_sig = 8'b00000010; end
+            8'b11111011: begin Y = 3'b010; i_sig = 8'b00000100; end
+            8'b11110111: begin Y = 3'b011; i_sig = 8'b00001000; end
+            8'b11101111: begin Y = 3'b100; i_sig = 8'b00010000; end
+            8'b11011111: begin Y = 3'b101; i_sig = 8'b00100000; end
+            8'b10111111: begin Y = 3'b110; i_sig = 8'b01000000; end
+            8'b01111111: begin Y = 3'b111; i_sig = 8'b10000000; end
+            default: out = 0;
+        endcase
+    end
+end
+SegDisplayCtrl unit (
+    .Y(Y),
+    .out(out),
+    .seg1(seg1),
+    .seg2(seg2)
+);
+always @(*) begin
+    seg_cs1 = 4'b0001;
+    seg_cs2 = 4'b0001;
+end
+endmodule