Initial commit
This commit is contained in:
61
Exp4/Exp4.runs/synth_1/.Xil/calc_propImpl.xdc
Normal file
61
Exp4/Exp4.runs/synth_1/.Xil/calc_propImpl.xdc
Normal file
@@ -0,0 +1,61 @@
|
||||
set_property SRC_FILE_INFO {cfile:F:/Schoolwork/DigitalLogic/Exp4/Exp4.srcs/constrs_1/new/calc.xdc rfile:../../../Exp4.srcs/constrs_1/new/calc.xdc id:1} [current_design]
|
||||
set_property src_info {type:XDC file:1 line:30 export:INPUT save:INPUT read:READ} [current_design]
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||||
set_property PACKAGE_PIN P5 [get_ports {data1[3]}]
|
||||
set_property src_info {type:XDC file:1 line:31 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PACKAGE_PIN P4 [get_ports {data1[2]}]
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||||
set_property src_info {type:XDC file:1 line:32 export:INPUT save:INPUT read:READ} [current_design]
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||||
set_property PACKAGE_PIN P3 [get_ports {data1[1]}]
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||||
set_property src_info {type:XDC file:1 line:33 export:INPUT save:INPUT read:READ} [current_design]
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||||
set_property PACKAGE_PIN P2 [get_ports {data1[0]}]
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||||
set_property src_info {type:XDC file:1 line:34 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PACKAGE_PIN R2 [get_ports {data2[3]}]
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||||
set_property src_info {type:XDC file:1 line:35 export:INPUT save:INPUT read:READ} [current_design]
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||||
set_property PACKAGE_PIN M4 [get_ports {data2[2]}]
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||||
set_property src_info {type:XDC file:1 line:36 export:INPUT save:INPUT read:READ} [current_design]
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||||
set_property PACKAGE_PIN N4 [get_ports {data2[1]}]
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||||
set_property src_info {type:XDC file:1 line:37 export:INPUT save:INPUT read:READ} [current_design]
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||||
set_property PACKAGE_PIN R1 [get_ports {data2[0]}]
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||||
set_property src_info {type:XDC file:1 line:38 export:INPUT save:INPUT read:READ} [current_design]
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||||
set_property PACKAGE_PIN F6 [get_ports {result[4]}]
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||||
set_property src_info {type:XDC file:1 line:39 export:INPUT save:INPUT read:READ} [current_design]
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||||
set_property PACKAGE_PIN G4 [get_ports {result[3]}]
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||||
set_property src_info {type:XDC file:1 line:40 export:INPUT save:INPUT read:READ} [current_design]
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||||
set_property PACKAGE_PIN G3 [get_ports {result[2]}]
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||||
set_property src_info {type:XDC file:1 line:41 export:INPUT save:INPUT read:READ} [current_design]
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||||
set_property PACKAGE_PIN J4 [get_ports {result[1]}]
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||||
set_property src_info {type:XDC file:1 line:42 export:INPUT save:INPUT read:READ} [current_design]
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||||
set_property PACKAGE_PIN H4 [get_ports {result[0]}]
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set_property src_info {type:XDC file:1 line:43 export:INPUT save:INPUT read:READ} [current_design]
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||||
set_property PACKAGE_PIN D4 [get_ports {seg[6]}]
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set_property src_info {type:XDC file:1 line:44 export:INPUT save:INPUT read:READ} [current_design]
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||||
set_property PACKAGE_PIN E3 [get_ports {seg[5]}]
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set_property src_info {type:XDC file:1 line:45 export:INPUT save:INPUT read:READ} [current_design]
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||||
set_property PACKAGE_PIN D3 [get_ports {seg[4]}]
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set_property src_info {type:XDC file:1 line:46 export:INPUT save:INPUT read:READ} [current_design]
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set_property PACKAGE_PIN F4 [get_ports {seg[3]}]
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set_property src_info {type:XDC file:1 line:47 export:INPUT save:INPUT read:READ} [current_design]
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set_property PACKAGE_PIN F3 [get_ports {seg[2]}]
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set_property src_info {type:XDC file:1 line:48 export:INPUT save:INPUT read:READ} [current_design]
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set_property PACKAGE_PIN E2 [get_ports {seg[1]}]
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set_property src_info {type:XDC file:1 line:49 export:INPUT save:INPUT read:READ} [current_design]
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||||
set_property PACKAGE_PIN D2 [get_ports {seg[0]}]
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||||
set_property src_info {type:XDC file:1 line:50 export:INPUT save:INPUT read:READ} [current_design]
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||||
set_property PACKAGE_PIN G1 [get_ports {seg_cs[3]}]
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||||
set_property src_info {type:XDC file:1 line:51 export:INPUT save:INPUT read:READ} [current_design]
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||||
set_property PACKAGE_PIN F1 [get_ports {seg_cs[2]}]
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||||
set_property src_info {type:XDC file:1 line:52 export:INPUT save:INPUT read:READ} [current_design]
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||||
set_property PACKAGE_PIN E1 [get_ports {seg_cs[1]}]
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set_property src_info {type:XDC file:1 line:53 export:INPUT save:INPUT read:READ} [current_design]
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||||
set_property PACKAGE_PIN G6 [get_ports {seg_cs[0]}]
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set_property src_info {type:XDC file:1 line:54 export:INPUT save:INPUT read:READ} [current_design]
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set_property PACKAGE_PIN U4 [get_ports {type[4]}]
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set_property src_info {type:XDC file:1 line:55 export:INPUT save:INPUT read:READ} [current_design]
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||||
set_property PACKAGE_PIN V1 [get_ports {type[3]}]
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||||
set_property src_info {type:XDC file:1 line:56 export:INPUT save:INPUT read:READ} [current_design]
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||||
set_property PACKAGE_PIN R15 [get_ports {type[2]}]
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||||
set_property src_info {type:XDC file:1 line:57 export:INPUT save:INPUT read:READ} [current_design]
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||||
set_property PACKAGE_PIN R11 [get_ports {type[1]}]
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||||
set_property src_info {type:XDC file:1 line:58 export:INPUT save:INPUT read:READ} [current_design]
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||||
set_property PACKAGE_PIN R17 [get_ports {type[0]}]
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set_property src_info {type:XDC file:1 line:60 export:INPUT save:INPUT read:READ} [current_design]
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||||
set_property PACKAGE_PIN P17 [get_ports clk]
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||||
BIN
Exp4/Exp4.runs/synth_1/calc.dcp
Normal file
BIN
Exp4/Exp4.runs/synth_1/calc.dcp
Normal file
Binary file not shown.
58
Exp4/Exp4.runs/synth_1/calc.tcl
Normal file
58
Exp4/Exp4.runs/synth_1/calc.tcl
Normal file
@@ -0,0 +1,58 @@
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||||
#
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||||
# Synthesis run script generated by Vivado
|
||||
#
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||||
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||||
proc create_report { reportName command } {
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||||
set status "."
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||||
append status $reportName ".fail"
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||||
if { [file exists $status] } {
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||||
eval file delete [glob $status]
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||||
}
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||||
send_msg_id runtcl-4 info "Executing : $command"
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||||
set retval [eval catch { $command } msg]
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||||
if { $retval != 0 } {
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||||
set fp [open $status w]
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||||
close $fp
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||||
send_msg_id runtcl-5 warning "$msg"
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||||
}
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||||
}
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||||
set_param xicom.use_bs_reader 1
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||||
create_project -in_memory -part xc7a35tcsg324-1
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||||
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||||
set_param project.singleFileAddWarning.threshold 0
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||||
set_param project.compositeFile.enableAutoGeneration 0
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||||
set_param synth.vivado.isSynthRun true
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||||
set_property webtalk.parent_dir F:/Schoolwork/DigitalLogic/Exp4/Exp4.cache/wt [current_project]
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||||
set_property parent.project_path F:/Schoolwork/DigitalLogic/Exp4/Exp4.xpr [current_project]
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||||
set_property default_lib xil_defaultlib [current_project]
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||||
set_property target_language Verilog [current_project]
|
||||
set_property ip_output_repo f:/Schoolwork/DigitalLogic/Exp4/Exp4.cache/ip [current_project]
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||||
set_property ip_cache_permissions {read write} [current_project]
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||||
read_verilog -library xil_defaultlib {
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||||
F:/Schoolwork/DigitalLogic/Exp4/Exp4.srcs/sources_1/new/SegDisplayCtrl.v
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||||
F:/Schoolwork/DigitalLogic/Exp4/Exp4.srcs/sources_1/new/judge.v
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||||
F:/Schoolwork/DigitalLogic/Exp4/Exp4.srcs/sources_1/new/calc.v
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||||
}
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||||
# Mark all dcp files as not used in implementation to prevent them from being
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||||
# stitched into the results of this synthesis run. Any black boxes in the
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||||
# design are intentionally left as such for best results. Dcp files will be
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||||
# stitched into the design at a later time, either when this synthesis run is
|
||||
# opened, or when it is stitched into a dependent implementation run.
|
||||
foreach dcp [get_files -quiet -all -filter file_type=="Design\ Checkpoint"] {
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||||
set_property used_in_implementation false $dcp
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||||
}
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||||
read_xdc F:/Schoolwork/DigitalLogic/Exp4/Exp4.srcs/constrs_1/new/calc.xdc
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||||
set_property used_in_implementation false [get_files F:/Schoolwork/DigitalLogic/Exp4/Exp4.srcs/constrs_1/new/calc.xdc]
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||||
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||||
set_param ips.enableIPCacheLiteLoad 0
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||||
close [open __synthesis_is_running__ w]
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||||
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synth_design -top calc -part xc7a35tcsg324-1
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||||
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||||
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# disable binary constraint mode for synth run checkpoints
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set_param constraints.enableBinaryConstraints false
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||||
write_checkpoint -force -noxdef calc.dcp
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||||
create_report "synth_1_synth_report_utilization_0" "report_utilization -file calc_utilization_synth.rpt -pb calc_utilization_synth.pb"
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||||
file delete __synthesis_is_running__
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||||
close [open __synthesis_is_complete__ w]
|
||||
306
Exp4/Exp4.runs/synth_1/calc.vds
Normal file
306
Exp4/Exp4.runs/synth_1/calc.vds
Normal file
@@ -0,0 +1,306 @@
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||||
#-----------------------------------------------------------
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||||
# Vivado v2018.1 (64-bit)
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||||
# SW Build 2188600 on Wed Apr 4 18:40:38 MDT 2018
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||||
# IP Build 2185939 on Wed Apr 4 20:55:05 MDT 2018
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||||
# Start of session at: Thu Nov 7 02:28:12 2024
|
||||
# Process ID: 21720
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||||
# Current directory: F:/Schoolwork/DigitalLogic/Exp4/Exp4.runs/synth_1
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||||
# Command line: vivado.exe -log calc.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source calc.tcl
|
||||
# Log file: F:/Schoolwork/DigitalLogic/Exp4/Exp4.runs/synth_1/calc.vds
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||||
# Journal file: F:/Schoolwork/DigitalLogic/Exp4/Exp4.runs/synth_1\vivado.jou
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||||
#-----------------------------------------------------------
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||||
source calc.tcl -notrace
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Command: synth_design -top calc -part xc7a35tcsg324-1
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||||
Starting synth_design
|
||||
Attempting to get a license for feature 'Synthesis' and/or device 'xc7a35t'
|
||||
INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7a35t'
|
||||
INFO: Launching helper process for spawning children vivado processes
|
||||
INFO: Helper process launched with PID 28152
|
||||
---------------------------------------------------------------------------------
|
||||
Starting RTL Elaboration : Time (s): cpu = 00:00:02 ; elapsed = 00:00:03 . Memory (MB): peak = 410.371 ; gain = 97.773
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||||
---------------------------------------------------------------------------------
|
||||
INFO: [Synth 8-6157] synthesizing module 'calc' [F:/Schoolwork/DigitalLogic/Exp4/Exp4.srcs/sources_1/new/calc.v:23]
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||||
INFO: [Synth 8-6157] synthesizing module 'judge' [F:/Schoolwork/DigitalLogic/Exp4/Exp4.srcs/sources_1/new/judge.v:23]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'judge' (1#1) [F:/Schoolwork/DigitalLogic/Exp4/Exp4.srcs/sources_1/new/judge.v:23]
|
||||
INFO: [Synth 8-6157] synthesizing module 'SegDisplayCtrl' [F:/Schoolwork/DigitalLogic/Exp4/Exp4.srcs/sources_1/new/SegDisplayCtrl.v:23]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'SegDisplayCtrl' (2#1) [F:/Schoolwork/DigitalLogic/Exp4/Exp4.srcs/sources_1/new/SegDisplayCtrl.v:23]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'calc' (3#1) [F:/Schoolwork/DigitalLogic/Exp4/Exp4.srcs/sources_1/new/calc.v:23]
|
||||
WARNING: [Synth 8-3917] design calc has port seg_cs[3] driven by constant 0
|
||||
WARNING: [Synth 8-3917] design calc has port seg_cs[2] driven by constant 0
|
||||
---------------------------------------------------------------------------------
|
||||
Finished RTL Elaboration : Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 465.418 ; gain = 152.820
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Report Check Netlist:
|
||||
+------+------------------+-------+---------+-------+------------------+
|
||||
| |Item |Errors |Warnings |Status |Description |
|
||||
+------+------------------+-------+---------+-------+------------------+
|
||||
|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets |
|
||||
+------+------------------+-------+---------+-------+------------------+
|
||||
---------------------------------------------------------------------------------
|
||||
Start Handling Custom Attributes
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Handling Custom Attributes : Time (s): cpu = 00:00:03 ; elapsed = 00:00:04 . Memory (MB): peak = 465.418 ; gain = 152.820
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:03 ; elapsed = 00:00:04 . Memory (MB): peak = 465.418 ; gain = 152.820
|
||||
---------------------------------------------------------------------------------
|
||||
INFO: [Device 21-403] Loading part xc7a35tcsg324-1
|
||||
INFO: [Project 1-570] Preparing netlist for logic optimization
|
||||
|
||||
Processing XDC Constraints
|
||||
Initializing timing engine
|
||||
Parsing XDC File [F:/Schoolwork/DigitalLogic/Exp4/Exp4.srcs/constrs_1/new/calc.xdc]
|
||||
Finished Parsing XDC File [F:/Schoolwork/DigitalLogic/Exp4/Exp4.srcs/constrs_1/new/calc.xdc]
|
||||
INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [F:/Schoolwork/DigitalLogic/Exp4/Exp4.srcs/constrs_1/new/calc.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/calc_propImpl.xdc].
|
||||
Resolution: To avoid this warning, move constraints listed in [.Xil/calc_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
|
||||
Completed Processing XDC Constraints
|
||||
|
||||
INFO: [Project 1-111] Unisim Transformation Summary:
|
||||
No Unisim elements were transformed.
|
||||
|
||||
Constraint Validation Runtime : Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 770.922 ; gain = 0.000
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 770.922 ; gain = 458.324
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Loading Part and Timing Information
|
||||
---------------------------------------------------------------------------------
|
||||
Loading part: xc7a35tcsg324-1
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 770.922 ; gain = 458.324
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Applying 'set_property' XDC Constraints
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 770.922 ; gain = 458.324
|
||||
---------------------------------------------------------------------------------
|
||||
INFO: [Synth 8-5587] ROM size for "seg" is below threshold of ROM address width. It will be mapped to LUTs
|
||||
WARNING: [Synth 8-327] inferring latch for variable 'result_reg' [F:/Schoolwork/DigitalLogic/Exp4/Exp4.srcs/sources_1/new/judge.v:29]
|
||||
---------------------------------------------------------------------------------
|
||||
Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 770.922 ; gain = 458.324
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Report RTL Partitions:
|
||||
+-+--------------+------------+----------+
|
||||
| |RTL Partition |Replication |Instances |
|
||||
+-+--------------+------------+----------+
|
||||
+-+--------------+------------+----------+
|
||||
---------------------------------------------------------------------------------
|
||||
Start RTL Component Statistics
|
||||
---------------------------------------------------------------------------------
|
||||
Detailed RTL Component Info :
|
||||
+---Adders :
|
||||
2 Input 5 Bit Adders := 1
|
||||
+---XORs :
|
||||
2 Input 5 Bit XORs := 1
|
||||
+---Registers :
|
||||
5 Bit Registers := 1
|
||||
+---Muxes :
|
||||
6 Input 7 Bit Muxes := 1
|
||||
3 Input 5 Bit Muxes := 1
|
||||
---------------------------------------------------------------------------------
|
||||
Finished RTL Component Statistics
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start RTL Hierarchical Component Statistics
|
||||
---------------------------------------------------------------------------------
|
||||
Hierarchical RTL Component report
|
||||
Module calc
|
||||
Detailed RTL Component Info :
|
||||
+---Adders :
|
||||
2 Input 5 Bit Adders := 1
|
||||
+---XORs :
|
||||
2 Input 5 Bit XORs := 1
|
||||
+---Registers :
|
||||
5 Bit Registers := 1
|
||||
Module judge
|
||||
Detailed RTL Component Info :
|
||||
+---Muxes :
|
||||
3 Input 5 Bit Muxes := 1
|
||||
Module SegDisplayCtrl
|
||||
Detailed RTL Component Info :
|
||||
+---Muxes :
|
||||
6 Input 7 Bit Muxes := 1
|
||||
---------------------------------------------------------------------------------
|
||||
Finished RTL Hierarchical Component Statistics
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Part Resource Summary
|
||||
---------------------------------------------------------------------------------
|
||||
Part Resources:
|
||||
DSPs: 90 (col length:60)
|
||||
BRAMs: 100 (col length: RAMB18 60 RAMB36 30)
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Part Resource Summary
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Cross Boundary and Area Optimization
|
||||
---------------------------------------------------------------------------------
|
||||
Warning: Parallel synthesis criteria is not met
|
||||
WARNING: [Synth 8-3917] design calc has port seg_cs[3] driven by constant 0
|
||||
WARNING: [Synth 8-3917] design calc has port seg_cs[2] driven by constant 0
|
||||
WARNING: [Synth 8-3917] design calc has port seg_cs[1] driven by constant 0
|
||||
INFO: [Synth 8-3886] merging instance 'run/result_reg[0]' (LDC) to 'run/result_reg[4]'
|
||||
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\run/result_reg[4] )
|
||||
WARNING: [Synth 8-3332] Sequential element (run/result_reg[4]) is unused and will be removed from module calc.
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:10 ; elapsed = 00:00:12 . Memory (MB): peak = 770.922 ; gain = 458.324
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Report RTL Partitions:
|
||||
+-+--------------+------------+----------+
|
||||
| |RTL Partition |Replication |Instances |
|
||||
+-+--------------+------------+----------+
|
||||
+-+--------------+------------+----------+
|
||||
---------------------------------------------------------------------------------
|
||||
Start Applying XDC Timing Constraints
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:15 ; elapsed = 00:00:18 . Memory (MB): peak = 786.383 ; gain = 473.785
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Timing Optimization
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Timing Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:18 . Memory (MB): peak = 786.383 ; gain = 473.785
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Report RTL Partitions:
|
||||
+-+--------------+------------+----------+
|
||||
| |RTL Partition |Replication |Instances |
|
||||
+-+--------------+------------+----------+
|
||||
+-+--------------+------------+----------+
|
||||
---------------------------------------------------------------------------------
|
||||
Start Technology Mapping
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Technology Mapping : Time (s): cpu = 00:00:15 ; elapsed = 00:00:18 . Memory (MB): peak = 786.754 ; gain = 474.156
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Report RTL Partitions:
|
||||
+-+--------------+------------+----------+
|
||||
| |RTL Partition |Replication |Instances |
|
||||
+-+--------------+------------+----------+
|
||||
+-+--------------+------------+----------+
|
||||
---------------------------------------------------------------------------------
|
||||
Start IO Insertion
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Flattening Before IO Insertion
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Flattening Before IO Insertion
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Final Netlist Cleanup
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Final Netlist Cleanup
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished IO Insertion : Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 787.883 ; gain = 475.285
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Report Check Netlist:
|
||||
+------+------------------+-------+---------+-------+------------------+
|
||||
| |Item |Errors |Warnings |Status |Description |
|
||||
+------+------------------+-------+---------+-------+------------------+
|
||||
|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets |
|
||||
+------+------------------+-------+---------+-------+------------------+
|
||||
---------------------------------------------------------------------------------
|
||||
Start Renaming Generated Instances
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Renaming Generated Instances : Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 787.883 ; gain = 475.285
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Report RTL Partitions:
|
||||
+-+--------------+------------+----------+
|
||||
| |RTL Partition |Replication |Instances |
|
||||
+-+--------------+------------+----------+
|
||||
+-+--------------+------------+----------+
|
||||
---------------------------------------------------------------------------------
|
||||
Start Rebuilding User Hierarchy
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 787.883 ; gain = 475.285
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Renaming Generated Ports
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Renaming Generated Ports : Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 787.883 ; gain = 475.285
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Handling Custom Attributes
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Handling Custom Attributes : Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 787.883 ; gain = 475.285
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Renaming Generated Nets
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Renaming Generated Nets : Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 787.883 ; gain = 475.285
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Writing Synthesis Report
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Report BlackBoxes:
|
||||
+-+--------------+----------+
|
||||
| |BlackBox name |Instances |
|
||||
+-+--------------+----------+
|
||||
+-+--------------+----------+
|
||||
|
||||
Report Cell Usage:
|
||||
+------+-----+------+
|
||||
| |Cell |Count |
|
||||
+------+-----+------+
|
||||
|1 |BUFG | 1|
|
||||
|2 |LUT2 | 4|
|
||||
|3 |LUT3 | 4|
|
||||
|4 |LUT4 | 2|
|
||||
|5 |LUT5 | 11|
|
||||
|6 |LUT6 | 12|
|
||||
|7 |FDRE | 5|
|
||||
|8 |LDC | 1|
|
||||
|9 |LDCP | 2|
|
||||
|10 |IBUF | 14|
|
||||
|11 |OBUF | 16|
|
||||
+------+-----+------+
|
||||
|
||||
Report Instance Areas:
|
||||
+------+---------+-------+------+
|
||||
| |Instance |Module |Cells |
|
||||
+------+---------+-------+------+
|
||||
|1 |top | | 72|
|
||||
|2 | run |judge | 18|
|
||||
+------+---------+-------+------+
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Writing Synthesis Report : Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 787.883 ; gain = 475.285
|
||||
---------------------------------------------------------------------------------
|
||||
Synthesis finished with 0 errors, 0 critical warnings and 5 warnings.
|
||||
Synthesis Optimization Runtime : Time (s): cpu = 00:00:10 ; elapsed = 00:00:14 . Memory (MB): peak = 787.938 ; gain = 169.836
|
||||
Synthesis Optimization Complete : Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 787.938 ; gain = 475.340
|
||||
INFO: [Project 1-571] Translating synthesized netlist
|
||||
INFO: [Netlist 29-17] Analyzing 17 Unisim elements for replacement
|
||||
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
|
||||
INFO: [Project 1-570] Preparing netlist for logic optimization
|
||||
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
|
||||
INFO: [Project 1-111] Unisim Transformation Summary:
|
||||
A total of 3 instances were transformed.
|
||||
LDC => LDCE: 1 instances
|
||||
LDCP => LDCP (GND, LUT3, LUT3, LDCE, VCC): 2 instances
|
||||
|
||||
INFO: [Common 17-83] Releasing license: Synthesis
|
||||
21 Infos, 7 Warnings, 0 Critical Warnings and 0 Errors encountered.
|
||||
synth_design completed successfully
|
||||
synth_design: Time (s): cpu = 00:00:17 ; elapsed = 00:00:21 . Memory (MB): peak = 804.738 ; gain = 504.793
|
||||
INFO: [Common 17-1381] The checkpoint 'F:/Schoolwork/DigitalLogic/Exp4/Exp4.runs/synth_1/calc.dcp' has been generated.
|
||||
INFO: [runtcl-4] Executing : report_utilization -file calc_utilization_synth.rpt -pb calc_utilization_synth.pb
|
||||
report_utilization: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.010 . Memory (MB): peak = 804.738 ; gain = 0.000
|
||||
INFO: [Common 17-206] Exiting Vivado at Thu Nov 7 02:28:37 2024...
|
||||
BIN
Exp4/Exp4.runs/synth_1/calc_utilization_synth.pb
Normal file
BIN
Exp4/Exp4.runs/synth_1/calc_utilization_synth.pb
Normal file
Binary file not shown.
177
Exp4/Exp4.runs/synth_1/calc_utilization_synth.rpt
Normal file
177
Exp4/Exp4.runs/synth_1/calc_utilization_synth.rpt
Normal file
@@ -0,0 +1,177 @@
|
||||
Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
|
||||
---------------------------------------------------------------------------------------------------
|
||||
| Tool Version : Vivado v.2018.1 (win64) Build 2188600 Wed Apr 4 18:40:38 MDT 2018
|
||||
| Date : Thu Nov 7 02:28:37 2024
|
||||
| Host : W10-20240912132 running 64-bit major release (build 9200)
|
||||
| Command : report_utilization -file calc_utilization_synth.rpt -pb calc_utilization_synth.pb
|
||||
| Design : calc
|
||||
| Device : 7a35tcsg324-1
|
||||
| Design State : Synthesized
|
||||
---------------------------------------------------------------------------------------------------
|
||||
|
||||
Utilization Design Information
|
||||
|
||||
Table of Contents
|
||||
-----------------
|
||||
1. Slice Logic
|
||||
1.1 Summary of Registers by Type
|
||||
2. Memory
|
||||
3. DSP
|
||||
4. IO and GT Specific
|
||||
5. Clocking
|
||||
6. Specific Feature
|
||||
7. Primitives
|
||||
8. Black Boxes
|
||||
9. Instantiated Netlists
|
||||
|
||||
1. Slice Logic
|
||||
--------------
|
||||
|
||||
+-------------------------+------+-------+-----------+-------+
|
||||
| Site Type | Used | Fixed | Available | Util% |
|
||||
+-------------------------+------+-------+-----------+-------+
|
||||
| Slice LUTs* | 33 | 0 | 20800 | 0.16 |
|
||||
| LUT as Logic | 33 | 0 | 20800 | 0.16 |
|
||||
| LUT as Memory | 0 | 0 | 9600 | 0.00 |
|
||||
| Slice Registers | 8 | 0 | 41600 | 0.02 |
|
||||
| Register as Flip Flop | 5 | 0 | 41600 | 0.01 |
|
||||
| Register as Latch | 3 | 0 | 41600 | <0.01 |
|
||||
| F7 Muxes | 0 | 0 | 16300 | 0.00 |
|
||||
| F8 Muxes | 0 | 0 | 8150 | 0.00 |
|
||||
+-------------------------+------+-------+-----------+-------+
|
||||
* Warning! The Final LUT count, after physical optimizations and full implementation, is typically lower. Run opt_design after synthesis, if not already completed, for a more realistic count.
|
||||
|
||||
|
||||
1.1 Summary of Registers by Type
|
||||
--------------------------------
|
||||
|
||||
+-------+--------------+-------------+--------------+
|
||||
| Total | Clock Enable | Synchronous | Asynchronous |
|
||||
+-------+--------------+-------------+--------------+
|
||||
| 2 | _ | - | - |
|
||||
| 0 | _ | - | Set |
|
||||
| 0 | _ | - | Reset |
|
||||
| 0 | _ | Set | - |
|
||||
| 0 | _ | Reset | - |
|
||||
| 0 | Yes | - | - |
|
||||
| 0 | Yes | - | Set |
|
||||
| 1 | Yes | - | Reset |
|
||||
| 0 | Yes | Set | - |
|
||||
| 5 | Yes | Reset | - |
|
||||
+-------+--------------+-------------+--------------+
|
||||
|
||||
|
||||
2. Memory
|
||||
---------
|
||||
|
||||
+----------------+------+-------+-----------+-------+
|
||||
| Site Type | Used | Fixed | Available | Util% |
|
||||
+----------------+------+-------+-----------+-------+
|
||||
| Block RAM Tile | 0 | 0 | 50 | 0.00 |
|
||||
| RAMB36/FIFO* | 0 | 0 | 50 | 0.00 |
|
||||
| RAMB18 | 0 | 0 | 100 | 0.00 |
|
||||
+----------------+------+-------+-----------+-------+
|
||||
* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1
|
||||
|
||||
|
||||
3. DSP
|
||||
------
|
||||
|
||||
+-----------+------+-------+-----------+-------+
|
||||
| Site Type | Used | Fixed | Available | Util% |
|
||||
+-----------+------+-------+-----------+-------+
|
||||
| DSPs | 0 | 0 | 90 | 0.00 |
|
||||
+-----------+------+-------+-----------+-------+
|
||||
|
||||
|
||||
4. IO and GT Specific
|
||||
---------------------
|
||||
|
||||
+-----------------------------+------+-------+-----------+-------+
|
||||
| Site Type | Used | Fixed | Available | Util% |
|
||||
+-----------------------------+------+-------+-----------+-------+
|
||||
| Bonded IOB | 30 | 0 | 210 | 14.29 |
|
||||
| Bonded IPADs | 0 | 0 | 2 | 0.00 |
|
||||
| PHY_CONTROL | 0 | 0 | 5 | 0.00 |
|
||||
| PHASER_REF | 0 | 0 | 5 | 0.00 |
|
||||
| OUT_FIFO | 0 | 0 | 20 | 0.00 |
|
||||
| IN_FIFO | 0 | 0 | 20 | 0.00 |
|
||||
| IDELAYCTRL | 0 | 0 | 5 | 0.00 |
|
||||
| IBUFDS | 0 | 0 | 202 | 0.00 |
|
||||
| PHASER_OUT/PHASER_OUT_PHY | 0 | 0 | 20 | 0.00 |
|
||||
| PHASER_IN/PHASER_IN_PHY | 0 | 0 | 20 | 0.00 |
|
||||
| IDELAYE2/IDELAYE2_FINEDELAY | 0 | 0 | 250 | 0.00 |
|
||||
| ILOGIC | 0 | 0 | 210 | 0.00 |
|
||||
| OLOGIC | 0 | 0 | 210 | 0.00 |
|
||||
+-----------------------------+------+-------+-----------+-------+
|
||||
|
||||
|
||||
5. Clocking
|
||||
-----------
|
||||
|
||||
+------------+------+-------+-----------+-------+
|
||||
| Site Type | Used | Fixed | Available | Util% |
|
||||
+------------+------+-------+-----------+-------+
|
||||
| BUFGCTRL | 1 | 0 | 32 | 3.13 |
|
||||
| BUFIO | 0 | 0 | 20 | 0.00 |
|
||||
| MMCME2_ADV | 0 | 0 | 5 | 0.00 |
|
||||
| PLLE2_ADV | 0 | 0 | 5 | 0.00 |
|
||||
| BUFMRCE | 0 | 0 | 10 | 0.00 |
|
||||
| BUFHCE | 0 | 0 | 72 | 0.00 |
|
||||
| BUFR | 0 | 0 | 20 | 0.00 |
|
||||
+------------+------+-------+-----------+-------+
|
||||
|
||||
|
||||
6. Specific Feature
|
||||
-------------------
|
||||
|
||||
+-------------+------+-------+-----------+-------+
|
||||
| Site Type | Used | Fixed | Available | Util% |
|
||||
+-------------+------+-------+-----------+-------+
|
||||
| BSCANE2 | 0 | 0 | 4 | 0.00 |
|
||||
| CAPTUREE2 | 0 | 0 | 1 | 0.00 |
|
||||
| DNA_PORT | 0 | 0 | 1 | 0.00 |
|
||||
| EFUSE_USR | 0 | 0 | 1 | 0.00 |
|
||||
| FRAME_ECCE2 | 0 | 0 | 1 | 0.00 |
|
||||
| ICAPE2 | 0 | 0 | 2 | 0.00 |
|
||||
| PCIE_2_1 | 0 | 0 | 1 | 0.00 |
|
||||
| STARTUPE2 | 0 | 0 | 1 | 0.00 |
|
||||
| XADC | 0 | 0 | 1 | 0.00 |
|
||||
+-------------+------+-------+-----------+-------+
|
||||
|
||||
|
||||
7. Primitives
|
||||
-------------
|
||||
|
||||
+----------+------+---------------------+
|
||||
| Ref Name | Used | Functional Category |
|
||||
+----------+------+---------------------+
|
||||
| OBUF | 16 | IO |
|
||||
| IBUF | 14 | IO |
|
||||
| LUT6 | 12 | LUT |
|
||||
| LUT5 | 11 | LUT |
|
||||
| LUT3 | 8 | LUT |
|
||||
| FDRE | 5 | Flop & Latch |
|
||||
| LUT2 | 4 | LUT |
|
||||
| LDCE | 3 | Flop & Latch |
|
||||
| LUT4 | 2 | LUT |
|
||||
| BUFG | 1 | Clock |
|
||||
+----------+------+---------------------+
|
||||
|
||||
|
||||
8. Black Boxes
|
||||
--------------
|
||||
|
||||
+----------+------+
|
||||
| Ref Name | Used |
|
||||
+----------+------+
|
||||
|
||||
|
||||
9. Instantiated Netlists
|
||||
------------------------
|
||||
|
||||
+----------+------+
|
||||
| Ref Name | Used |
|
||||
+----------+------+
|
||||
|
||||
|
||||
55
Exp4/Exp4.runs/synth_1/gen_run.xml
Normal file
55
Exp4/Exp4.runs/synth_1/gen_run.xml
Normal file
@@ -0,0 +1,55 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<GenRun Id="synth_1" LaunchPart="xc7a35tcsg324-1" LaunchTime="1730917691">
|
||||
<File Type="PA-TCL" Name="calc.tcl"/>
|
||||
<File Type="REPORTS-TCL" Name="calc_reports.tcl"/>
|
||||
<File Type="RDS-RDS" Name="calc.vds"/>
|
||||
<File Type="RDS-UTIL" Name="calc_utilization_synth.rpt"/>
|
||||
<File Type="RDS-UTIL-PB" Name="calc_utilization_synth.pb"/>
|
||||
<File Type="RDS-DCP" Name="calc.dcp"/>
|
||||
<FileSet Name="sources" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1">
|
||||
<Filter Type="Srcs"/>
|
||||
<File Path="$PSRCDIR/sources_1/new/SegDisplayCtrl.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PSRCDIR/sources_1/new/judge.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PSRCDIR/sources_1/new/calc.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<Config>
|
||||
<Option Name="DesignMode" Val="RTL"/>
|
||||
<Option Name="TopModule" Val="calc"/>
|
||||
<Option Name="TopAutoSet" Val="TRUE"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="constrs_in" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1">
|
||||
<Filter Type="Constrs"/>
|
||||
<File Path="$PSRCDIR/constrs_1/new/calc.xdc">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<Config>
|
||||
<Option Name="TargetConstrsFile" Val="$PSRCDIR/constrs_1/new/calc.xdc"/>
|
||||
<Option Name="ConstrsType" Val="XDC"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2018"/>
|
||||
<Step Id="synth_design"/>
|
||||
</Strategy>
|
||||
</GenRun>
|
||||
9
Exp4/Exp4.runs/synth_1/htr.txt
Normal file
9
Exp4/Exp4.runs/synth_1/htr.txt
Normal file
@@ -0,0 +1,9 @@
|
||||
REM
|
||||
REM Vivado(TM)
|
||||
REM htr.txt: a Vivado-generated description of how-to-repeat the
|
||||
REM the basic steps of a run. Note that runme.bat/sh needs
|
||||
REM to be invoked for Vivado to track run status.
|
||||
REM Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
|
||||
REM
|
||||
|
||||
vivado -log calc.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source calc.tcl
|
||||
12
Exp4/Exp4.runs/synth_1/vivado.jou
Normal file
12
Exp4/Exp4.runs/synth_1/vivado.jou
Normal file
@@ -0,0 +1,12 @@
|
||||
#-----------------------------------------------------------
|
||||
# Vivado v2018.1 (64-bit)
|
||||
# SW Build 2188600 on Wed Apr 4 18:40:38 MDT 2018
|
||||
# IP Build 2185939 on Wed Apr 4 20:55:05 MDT 2018
|
||||
# Start of session at: Thu Nov 7 02:28:12 2024
|
||||
# Process ID: 21720
|
||||
# Current directory: F:/Schoolwork/DigitalLogic/Exp4/Exp4.runs/synth_1
|
||||
# Command line: vivado.exe -log calc.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source calc.tcl
|
||||
# Log file: F:/Schoolwork/DigitalLogic/Exp4/Exp4.runs/synth_1/calc.vds
|
||||
# Journal file: F:/Schoolwork/DigitalLogic/Exp4/Exp4.runs/synth_1\vivado.jou
|
||||
#-----------------------------------------------------------
|
||||
source calc.tcl -notrace
|
||||
BIN
Exp4/Exp4.runs/synth_1/vivado.pb
Normal file
BIN
Exp4/Exp4.runs/synth_1/vivado.pb
Normal file
Binary file not shown.
Reference in New Issue
Block a user