Initial commit

2025-11-06 10:08:01 +08:00
commit 0bded5b86e
1033 changed files with 55966 additions and 0 deletions
--- a/Exp4/Exp4.srcs/constrs_1/new/calc.xdc
+++ b/Exp4/Exp4.srcs/constrs_1/new/calc.xdc
@@ -0,0 +1,61 @@
+set_property IOSTANDARD LVCMOS33 [get_ports {data1[3]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {data1[2]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {data1[1]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {data1[0]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {data2[3]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {data2[2]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {data2[1]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {data2[0]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {result[4]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {result[3]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {result[2]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {result[1]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {result[0]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {seg[6]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {seg[5]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {seg[4]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {seg[3]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {seg[2]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {seg[1]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {seg[0]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {seg_cs[3]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {seg_cs[2]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {seg_cs[1]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {seg_cs[0]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {type[4]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {type[3]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {type[2]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {type[1]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {type[0]}]
+set_property PACKAGE_PIN P5 [get_ports {data1[3]}]
+set_property PACKAGE_PIN P4 [get_ports {data1[2]}]
+set_property PACKAGE_PIN P3 [get_ports {data1[1]}]
+set_property PACKAGE_PIN P2 [get_ports {data1[0]}]
+set_property PACKAGE_PIN R2 [get_ports {data2[3]}]
+set_property PACKAGE_PIN M4 [get_ports {data2[2]}]
+set_property PACKAGE_PIN N4 [get_ports {data2[1]}]
+set_property PACKAGE_PIN R1 [get_ports {data2[0]}]
+set_property PACKAGE_PIN F6 [get_ports {result[4]}]
+set_property PACKAGE_PIN G4 [get_ports {result[3]}]
+set_property PACKAGE_PIN G3 [get_ports {result[2]}]
+set_property PACKAGE_PIN J4 [get_ports {result[1]}]
+set_property PACKAGE_PIN H4 [get_ports {result[0]}]
+set_property PACKAGE_PIN D4 [get_ports {seg[6]}]
+set_property PACKAGE_PIN E3 [get_ports {seg[5]}]
+set_property PACKAGE_PIN D3 [get_ports {seg[4]}]
+set_property PACKAGE_PIN F4 [get_ports {seg[3]}]
+set_property PACKAGE_PIN F3 [get_ports {seg[2]}]
+set_property PACKAGE_PIN E2 [get_ports {seg[1]}]
+set_property PACKAGE_PIN D2 [get_ports {seg[0]}]
+set_property PACKAGE_PIN G1 [get_ports {seg_cs[3]}]
+set_property PACKAGE_PIN F1 [get_ports {seg_cs[2]}]
+set_property PACKAGE_PIN E1 [get_ports {seg_cs[1]}]
+set_property PACKAGE_PIN G6 [get_ports {seg_cs[0]}]
+set_property PACKAGE_PIN U4 [get_ports {type[4]}]
+set_property PACKAGE_PIN V1 [get_ports {type[3]}]
+set_property PACKAGE_PIN R15 [get_ports {type[2]}]
+set_property PACKAGE_PIN R11 [get_ports {type[1]}]
+set_property PACKAGE_PIN R17 [get_ports {type[0]}]
+
+set_property PACKAGE_PIN P17 [get_ports clk]
+set_property IOSTANDARD LVCMOS33 [get_ports clk]
--- a/Exp4/Exp4.srcs/sim_1/new/calc_tb.v
+++ b/Exp4/Exp4.srcs/sim_1/new/calc_tb.v
@@ -0,0 +1,60 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date: 2024/11/13 22:21:16
+// Design Name: 
+// Module Name: calc_tb
+// Project Name: 
+// Target Devices: 
+// Tool Versions: 
+// Description: 
+// 
+// Dependencies: 
+// 
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+// 
+//////////////////////////////////////////////////////////////////////////////////
+
+
+module calc_tb();
+    reg [3:0] data1;
+    reg [3:0] data2;
+    reg [4:0] type;
+    reg clk;
+    wire [4:0] result;
+    wire [6:0] seg;
+    wire [3:0] seg_cs;
+    calc uut (
+        .data1(data1),
+        .data2(data2),
+        .type(type),
+        .clk(clk),
+        .result(result),
+        .seg(seg),
+        .seg_cs(seg_cs)
+    );
+    initial begin
+        clk = 0;
+        forever #5 clk = ~clk; // Clock signal
+    end
+    initial begin
+        data1 = 4'b0011;
+        data2 = 4'b0101;
+        type = 5'b10000; #10; // Plus
+        type = 5'b01000; #10; // AND
+        type = 5'b00100; #10; // OR
+        type = 5'b00010; #10; // XOR
+        type = 5'b00001; #10; // Judge 1 <
+        data1 = 4'b0101;
+        data2 = 4'b0011;
+        type = 5'b00001; #10; // Judge 2 >
+        data1 = 4'b0101;
+        data2 = 4'b0101;
+        type = 5'b00001; #10; // Judge 3 =
+        $stop;
+    end
+endmodule
--- a/Exp4/Exp4.srcs/sources_1/new/SegDisplayCtrl.v
+++ b/Exp4/Exp4.srcs/sources_1/new/SegDisplayCtrl.v
@@ -0,0 +1,37 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date: 2024/10/31 11:26:14
+// Design Name: 
+// Module Name: SegDisplayCtrl
+// Project Name: 
+// Target Devices: 
+// Tool Versions: 
+// Description: 
+// 
+// Dependencies: 
+// 
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+// 
+//////////////////////////////////////////////////////////////////////////////////
+
+
+module SegDisplayCtrl(
+    input wire [4:0] type,
+    output reg [6:0] seg
+);
+always @(*) begin
+    case (type)
+        5'b10000: seg = 7'b1110111;  // a
+        5'b01000: seg = 7'b0011111;  // b
+        5'b00100: seg = 7'b1001110;  // c
+        5'b00010: seg = 7'b0111101;  // d
+        5'b00001: seg = 7'b1001111;  // e
+        default: seg = 7'b0000000;
+    endcase
+end
+endmodule
--- a/Exp4/Exp4.srcs/sources_1/new/calc.v
+++ b/Exp4/Exp4.srcs/sources_1/new/calc.v
@@ -0,0 +1,51 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date: 2024/10/31 10:43:01
+// Design Name: 
+// Module Name: calc
+// Project Name: 
+// Target Devices: 
+// Tool Versions: 
+// Description: 
+// 
+// Dependencies: 
+// 
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+// 
+//////////////////////////////////////////////////////////////////////////////////
+
+
+module calc(
+    input [3:0] data1,
+    input [3:0] data2,
+    input [4:0] type,
+    input clk,
+    output reg [4:0] result,
+    output wire [6:0] seg,
+    output reg [3:0] seg_cs
+);
+reg [4:0] stored_type = 5'b00000;
+wire [4:0] judge_result;
+wire [4:0] operation_result;
+judge run (.data1(data1), .data2(data2), .result(judge_result));
+always @(posedge clk) begin
+    if (type != 5'b00000) stored_type <= type;
+end
+always @(*) begin
+    case (stored_type)
+        5'b10000: result = data1 + data2;
+        5'b01000: result = data1 & data2;
+        5'b00100: result = data1 | data2;
+        5'b00010: result = data1 ^ data2;
+        5'b00001: result = judge_result;
+        default: result = 5'b00000;
+    endcase
+    seg_cs = (stored_type != 5'b00000) ? 4'b0001 : 4'b0000;
+end
+SegDisplayCtrl unit (.type(stored_type), .seg(seg));
+endmodule
--- a/Exp4/Exp4.srcs/sources_1/new/judge.v
+++ b/Exp4/Exp4.srcs/sources_1/new/judge.v
@@ -0,0 +1,33 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date: 2024/10/31 11:22:30
+// Design Name: 
+// Module Name: judge
+// Project Name: 
+// Target Devices: 
+// Tool Versions: 
+// Description: 
+// 
+// Dependencies: 
+// 
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+// 
+//////////////////////////////////////////////////////////////////////////////////
+
+
+module judge(
+    input [3:0] data1,
+    input [3:0] data2,
+    output reg [4:0] result
+);
+always @(*) begin
+    if (data1 > data2) result = 4'b1000;
+    else if (data1 < data2) result = 4'b0100;
+    else if (data1 == data2) result = 4'b0010;
+end
+endmodule