Initial commit

Exp4/Exp4.srcs/sim_1/new/calc_tb.v

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+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date: 2024/11/13 22:21:16
+// Design Name: 
+// Module Name: calc_tb
+// Project Name: 
+// Target Devices: 
+// Tool Versions: 
+// Description: 
+// 
+// Dependencies: 
+// 
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+// 
+//////////////////////////////////////////////////////////////////////////////////
+
+
+module calc_tb();
+    reg [3:0] data1;
+    reg [3:0] data2;
+    reg [4:0] type;
+    reg clk;
+    wire [4:0] result;
+    wire [6:0] seg;
+    wire [3:0] seg_cs;
+    calc uut (
+        .data1(data1),
+        .data2(data2),
+        .type(type),
+        .clk(clk),
+        .result(result),
+        .seg(seg),
+        .seg_cs(seg_cs)
+    );
+    initial begin
+        clk = 0;
+        forever #5 clk = ~clk; // Clock signal
+    end
+    initial begin
+        data1 = 4'b0011;
+        data2 = 4'b0101;
+        type = 5'b10000; #10; // Plus
+        type = 5'b01000; #10; // AND
+        type = 5'b00100; #10; // OR
+        type = 5'b00010; #10; // XOR
+        type = 5'b00001; #10; // Judge 1 <
+        data1 = 4'b0101;
+        data2 = 4'b0011;
+        type = 5'b00001; #10; // Judge 2 >
+        data1 = 4'b0101;
+        data2 = 4'b0101;
+        type = 5'b00001; #10; // Judge 3 =
+        $stop;
+    end
+endmodule