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`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2024/10/31 11:26:14
// Design Name:
// Module Name: SegDisplayCtrl
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module SegDisplayCtrl(
input wire [4:0] type,
output reg [6:0] seg
);
always @(*) begin
case (type)
5'b10000: seg = 7'b1110111; // a
5'b01000: seg = 7'b0011111; // b
5'b00100: seg = 7'b1001110; // c
5'b00010: seg = 7'b0111101; // d
5'b00001: seg = 7'b1001111; // e
default: seg = 7'b0000000;
endcase
end
endmodule

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`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2024/10/31 10:43:01
// Design Name:
// Module Name: calc
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module calc(
input [3:0] data1,
input [3:0] data2,
input [4:0] type,
input clk,
output reg [4:0] result,
output wire [6:0] seg,
output reg [3:0] seg_cs
);
reg [4:0] stored_type = 5'b00000;
wire [4:0] judge_result;
wire [4:0] operation_result;
judge run (.data1(data1), .data2(data2), .result(judge_result));
always @(posedge clk) begin
if (type != 5'b00000) stored_type <= type;
end
always @(*) begin
case (stored_type)
5'b10000: result = data1 + data2;
5'b01000: result = data1 & data2;
5'b00100: result = data1 | data2;
5'b00010: result = data1 ^ data2;
5'b00001: result = judge_result;
default: result = 5'b00000;
endcase
seg_cs = (stored_type != 5'b00000) ? 4'b0001 : 4'b0000;
end
SegDisplayCtrl unit (.type(stored_type), .seg(seg));
endmodule

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`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2024/10/31 11:22:30
// Design Name:
// Module Name: judge
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module judge(
input [3:0] data1,
input [3:0] data2,
output reg [4:0] result
);
always @(*) begin
if (data1 > data2) result = 4'b1000;
else if (data1 < data2) result = 4'b0100;
else if (data1 == data2) result = 4'b0010;
end
endmodule