Initial commit

Exp5-2-2/Exp5-2-2.srcs/sim_1/new/AsyncDFlipFlop_tb.v

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+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date: 2024/11/27 04:01:26
+// Design Name: 
+// Module Name: AsyncDFlipFlop_tb
+// Project Name: 
+// Target Devices: 
+// Tool Versions: 
+// Description: 
+// 
+// Dependencies: 
+// 
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+// 
+//////////////////////////////////////////////////////////////////////////////////
+
+
+module AsyncDFlipFlop_tb;
+reg D, clk, rst, set;
+wire Q;
+AsyncDFlipFlop uut (
+    .D(D),
+    .clk(clk),
+    .rst(rst),
+    .set(set),
+    .Q(Q)
+);
+initial begin
+    clk = 0;
+    forever #10 clk = ~clk;
+end
+initial begin
+    D = 0; rst = 0; set = 0; #15;
+    // Reset test
+    rst = 1; #20;
+    rst = 0; #20;
+    // Set test
+    set = 1; #20;
+    set = 0; #20;
+    // Data input test
+    D = 1; #30;
+    D = 0; #30;
+    $stop;
+end
+endmodule
+

Exp5-2-2/Exp5-2-2.srcs/sources_1/new/AsyncDFlipFlop.v

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+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date: 2024/11/24 23:40:16
+// Design Name: 
+// Module Name: AsyncDFlipFlop
+// Project Name: 
+// Target Devices: 
+// Tool Versions: 
+// Description: 
+// 
+// Dependencies: 
+// 
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+// 
+//////////////////////////////////////////////////////////////////////////////////
+
+
+module AsyncDFlipFlop (
+    input wire D,
+    input wire clk,
+    input wire rst,
+    input wire set,
+    output reg Q
+);
+always @(posedge clk or posedge rst or posedge set) begin
+    if (rst)
+        Q <= 0; // Reset Q clear
+    else if (set)
+        Q <= 1; // Set Q = 1
+    else
+        Q <= D;
+end
+endmodule