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Exp5-2-2/Exp5-2-2.srcs/sources_1/new/AsyncDFlipFlop.v

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+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date: 2024/11/24 23:40:16
+// Design Name: 
+// Module Name: AsyncDFlipFlop
+// Project Name: 
+// Target Devices: 
+// Tool Versions: 
+// Description: 
+// 
+// Dependencies: 
+// 
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+// 
+//////////////////////////////////////////////////////////////////////////////////
+
+
+module AsyncDFlipFlop (
+    input wire D,
+    input wire clk,
+    input wire rst,
+    input wire set,
+    output reg Q
+);
+always @(posedge clk or posedge rst or posedge set) begin
+    if (rst)
+        Q <= 0; // Reset Q clear
+    else if (set)
+        Q <= 1; // Set Q = 1
+    else
+        Q <= D;
+end
+endmodule