Initial commit

Exp6-1/Exp6-1.srcs/constrs_1/new/counter_19.xdc

@@ -0,0 +1,28 @@
+set_property IOSTANDARD LVCMOS33 [get_ports {din[3]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {din[2]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {din[1]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {din[0]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {qout[3]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {qout[2]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {qout[1]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {qout[0]}]
+set_property PACKAGE_PIN P5 [get_ports {din[3]}]
+set_property PACKAGE_PIN P4 [get_ports {din[2]}]
+set_property PACKAGE_PIN P3 [get_ports {din[1]}]
+set_property PACKAGE_PIN P2 [get_ports {din[0]}]
+set_property PACKAGE_PIN F6 [get_ports {qout[3]}]
+set_property PACKAGE_PIN G4 [get_ports {qout[2]}]
+set_property PACKAGE_PIN G3 [get_ports {qout[1]}]
+set_property PACKAGE_PIN J4 [get_ports {qout[0]}]
+set_property IOSTANDARD LVCMOS33 [get_ports clk]
+set_property IOSTANDARD LVCMOS33 [get_ports clrn]
+set_property IOSTANDARD LVCMOS33 [get_ports enp]
+set_property IOSTANDARD LVCMOS33 [get_ports ent]
+set_property IOSTANDARD LVCMOS33 [get_ports ldn]
+set_property IOSTANDARD LVCMOS33 [get_ports rco]
+set_property PACKAGE_PIN P17 [get_ports clk]
+set_property PACKAGE_PIN R1 [get_ports clrn]
+set_property PACKAGE_PIN N4 [get_ports enp]
+set_property PACKAGE_PIN M4 [get_ports ent]
+set_property PACKAGE_PIN R2 [get_ports ldn]
+set_property PACKAGE_PIN K2 [get_ports rco]

Exp6-1/Exp6-1.srcs/sim_1/new/counter_10_tb.v

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+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date: 2024/12/01 23:02:08
+// Design Name: 
+// Module Name: counter_10_tb
+// Project Name: 
+// Target Devices: 
+// Tool Versions: 
+// Description: 
+// 
+// Dependencies: 
+// 
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+// 
+//////////////////////////////////////////////////////////////////////////////////
+
+module counter_10_tb;
+reg clrn, clk, enp, ldn, ent;
+reg [3:0] din;
+wire [3:0] qout;
+wire rco;
+counter_10 dut (
+    .clrn(clrn), 
+    .clk(clk),
+    .enp(enp),
+    .ent(ent),
+    .ldn(ldn),
+    .din(din),
+    .qout(qout),
+    .rco(rco)
+);
+always #5 clk = ~clk;
+initial begin
+    // Initialize inputs
+    clrn = 1'b1;
+    clk = 1'b0;
+    enp = 1'b0;
+    ent = 1'b1;
+    ldn = 1'b1;
+    din = 4'b0000;
+    // Test async reset
+    #10 clrn = 1'b0;
+    #10 clrn = 1'b1;
+    // Test async preset
+    #10 ldn = 1'b0;
+    din = 4'b1001;
+    #10 ldn = 1'b1;
+    // Test counting up
+    #10 enp = 1'b1;
+    repeat (15) #10;
+    // Test holding
+    #10 enp = 1'b0;
+    repeat (5) #10;
+    $finish;
+end
+endmodule

Exp6-1/Exp6-1.srcs/sources_1/new/counter_10.v

@@ -0,0 +1,49 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date: 2024/12/01 22:50:46
+// Design Name: 
+// Module Name: counter_10
+// Project Name: 
+// Target Devices: 
+// Tool Versions: 
+// Description: 
+// 
+// Dependencies: 
+// 
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+// 
+//////////////////////////////////////////////////////////////////////////////////
+
+
+module counter_10 (clrn, clk, enp, ent, ldn, din, qout, rco);
+    // clrn: Asynchronous clear (active low)
+    // clk: Clock signal
+    // ent: Enable counting terminal
+    // enp: Enable counting parallel
+    // ldn: Load enable (active low)
+    // din: Input data
+    // qout: Current counter value
+    // rco: Ripple Carry Out
+    parameter din_width = 'd4;
+    parameter qout_width = 'd4;
+    parameter counter_size = 'd10;
+    input clrn, clk, ent, enp, ldn;
+    input [din_width - 1 : 0] din;
+    output [qout_width - 1 : 0] qout;
+    output rco;
+    reg [qout_width - 1 : 0] qout;
+    always @(posedge clk or negedge clrn) begin
+        if (~clrn) qout <= 0; // Async clear
+        else if (!ldn) qout <= din; // Async preset initial value
+        else if (enp && ent == 1)
+            if (qout == counter_size - 1) qout <= 0; // If maximum clear
+            else qout <= qout + 1; // Counter ++
+        else qout <= qout; // Keep
+    end
+    assign rco = (qout == counter_size - 1 && ent) ? 1 : 0; // Output highest bit
+endmodule

Exp6-1/Exp6-1.srcs/sources_1/new/counter_10_alt.v

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+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date: 2024/12/02 11:13:43
+// Design Name: 
+// Module Name: counter_10_alt
+// Project Name: 
+// Target Devices: 
+// Tool Versions: 
+// Description: 
+// 
+// Dependencies: 
+// 
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+// 
+//////////////////////////////////////////////////////////////////////////////////
+
+module counter_10_alt(
+    input wire clk,
+    input wire rst,
+    output reg [3:0] count
+);
+always @(posedge clk or posedge rst) begin
+    if (rst)
+        count <= 4'b0000;
+    else
+        count <= count + 1;
+end
+endmodule