Initial commit

Exp6-1/Exp6-1.srcs/sources_1/new/counter_10.v

@@ -0,0 +1,49 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date: 2024/12/01 22:50:46
+// Design Name: 
+// Module Name: counter_10
+// Project Name: 
+// Target Devices: 
+// Tool Versions: 
+// Description: 
+// 
+// Dependencies: 
+// 
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+// 
+//////////////////////////////////////////////////////////////////////////////////
+
+
+module counter_10 (clrn, clk, enp, ent, ldn, din, qout, rco);
+    // clrn: Asynchronous clear (active low)
+    // clk: Clock signal
+    // ent: Enable counting terminal
+    // enp: Enable counting parallel
+    // ldn: Load enable (active low)
+    // din: Input data
+    // qout: Current counter value
+    // rco: Ripple Carry Out
+    parameter din_width = 'd4;
+    parameter qout_width = 'd4;
+    parameter counter_size = 'd10;
+    input clrn, clk, ent, enp, ldn;
+    input [din_width - 1 : 0] din;
+    output [qout_width - 1 : 0] qout;
+    output rco;
+    reg [qout_width - 1 : 0] qout;
+    always @(posedge clk or negedge clrn) begin
+        if (~clrn) qout <= 0; // Async clear
+        else if (!ldn) qout <= din; // Async preset initial value
+        else if (enp && ent == 1)
+            if (qout == counter_size - 1) qout <= 0; // If maximum clear
+            else qout <= qout + 1; // Counter ++
+        else qout <= qout; // Keep
+    end
+    assign rco = (qout == counter_size - 1 && ent) ? 1 : 0; // Output highest bit
+endmodule

Exp6-1/Exp6-1.srcs/sources_1/new/counter_10_alt.v

@@ -0,0 +1,33 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date: 2024/12/02 11:13:43
+// Design Name: 
+// Module Name: counter_10_alt
+// Project Name: 
+// Target Devices: 
+// Tool Versions: 
+// Description: 
+// 
+// Dependencies: 
+// 
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+// 
+//////////////////////////////////////////////////////////////////////////////////
+
+module counter_10_alt(
+    input wire clk,
+    input wire rst,
+    output reg [3:0] count
+);
+always @(posedge clk or posedge rst) begin
+    if (rst)
+        count <= 4'b0000;
+    else
+        count <= count + 1;
+end
+endmodule