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2025-11-06 10:08:01 +08:00
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13
Exp6-2/Exp6-2.runs/synth_1/.Xil/slowClock_propImpl.xdc Normal file
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set_property SRC_FILE_INFO {cfile:F:/Schoolwork/DigitalLogic/Exp6-2/Exp6-2.srcs/constrs_1/new/slowClock.xdc rfile:../../../Exp6-2.srcs/constrs_1/new/slowClock.xdc id:1} [current_design]
set_property src_info {type:XDC file:1 line:7 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN P17 [get_ports clk]
set_property src_info {type:XDC file:1 line:8 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN R1 [get_ports reset]
set_property src_info {type:XDC file:1 line:9 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN G3 [get_ports clk_1Hz]
set_property src_info {type:XDC file:1 line:10 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN J4 [get_ports clk_12Hz]
set_property src_info {type:XDC file:1 line:11 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN H4 [get_ports clk_48Hz]
set_property src_info {type:XDC file:1 line:12 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN J3 [get_ports clk_190Hz]

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Exp6-2/Exp6-2.runs/synth_1/gen_run.xml Normal file
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<?xml version="1.0" encoding="UTF-8"?>
<GenRun Id="synth_1" LaunchPart="xc7a35tcsg324-1" LaunchTime="1734005496">
<File Type="PA-TCL" Name="slowClock.tcl"/>
<File Type="RDS-PROPCONSTRS" Name="slowClock_drc_synth.rpt"/>
<File Type="REPORTS-TCL" Name="slowClock_reports.tcl"/>
<File Type="RDS-RDS" Name="slowClock.vds"/>
<File Type="RDS-UTIL" Name="slowClock_utilization_synth.rpt"/>
<File Type="RDS-UTIL-PB" Name="slowClock_utilization_synth.pb"/>
<File Type="RDS-DCP" Name="slowClock.dcp"/>
<File Type="VDS-TIMINGSUMMARY" Name="slowClock_timing_summary_synth.rpt"/>
<File Type="VDS-TIMING-PB" Name="slowClock_timing_summary_synth.pb"/>
<FileSet Name="sources" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1">
<Filter Type="Srcs"/>
<File Path="$PSRCDIR/sources_1/new/slowClock.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<Config>
<Option Name="DesignMode" Val="RTL"/>
<Option Name="TopModule" Val="slowClock"/>
<Option Name="TopAutoSet" Val="TRUE"/>
</Config>
</FileSet>
<FileSet Name="constrs_in" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1">
<Filter Type="Constrs"/>
<File Path="$PSRCDIR/constrs_1/new/slowClock.xdc">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
</FileInfo>
</File>
<Config>
<Option Name="TargetConstrsFile" Val="$PSRCDIR/constrs_1/new/slowClock.xdc"/>
<Option Name="ConstrsType" Val="XDC"/>
</Config>
</FileSet>
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2018"/>
<Step Id="synth_design"/>
</Strategy>
</GenRun>

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Exp6-2/Exp6-2.runs/synth_1/htr.txt Normal file
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REM
REM Vivado(TM)
REM htr.txt: a Vivado-generated description of how-to-repeat the
REM the basic steps of a run. Note that runme.bat/sh needs
REM to be invoked for Vivado to track run status.
REM Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
REM
vivado -log slowClock.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source slowClock.tcl

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Exp6-2/Exp6-2.runs/synth_1/slowClock.dcp Normal file
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Exp6-2/Exp6-2.runs/synth_1/slowClock.tcl Normal file
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#
# Synthesis run script generated by Vivado
#
proc create_report { reportName command } {
set status "."
append status $reportName ".fail"
if { [file exists $status] } {
eval file delete [glob $status]
}
send_msg_id runtcl-4 info "Executing : $command"
set retval [eval catch { $command } msg]
if { $retval != 0 } {
set fp [open $status w]
close $fp
send_msg_id runtcl-5 warning "$msg"
}
}
set_param xicom.use_bs_reader 1
create_project -in_memory -part xc7a35tcsg324-1
set_param project.singleFileAddWarning.threshold 0
set_param project.compositeFile.enableAutoGeneration 0
set_param synth.vivado.isSynthRun true
set_property webtalk.parent_dir F:/Schoolwork/DigitalLogic/Exp6-2/Exp6-2.cache/wt [current_project]
set_property parent.project_path F:/Schoolwork/DigitalLogic/Exp6-2/Exp6-2.xpr [current_project]
set_property default_lib xil_defaultlib [current_project]
set_property target_language Verilog [current_project]
set_property ip_output_repo f:/Schoolwork/DigitalLogic/Exp6-2/Exp6-2.cache/ip [current_project]
set_property ip_cache_permissions {read write} [current_project]
read_verilog -library xil_defaultlib F:/Schoolwork/DigitalLogic/Exp6-2/Exp6-2.srcs/sources_1/new/slowClock.v
# Mark all dcp files as not used in implementation to prevent them from being
# stitched into the results of this synthesis run. Any black boxes in the
# design are intentionally left as such for best results. Dcp files will be
# stitched into the design at a later time, either when this synthesis run is
# opened, or when it is stitched into a dependent implementation run.
foreach dcp [get_files -quiet -all -filter file_type=="Design\ Checkpoint"] {
set_property used_in_implementation false $dcp
}
read_xdc F:/Schoolwork/DigitalLogic/Exp6-2/Exp6-2.srcs/constrs_1/new/slowClock.xdc
set_property used_in_implementation false [get_files F:/Schoolwork/DigitalLogic/Exp6-2/Exp6-2.srcs/constrs_1/new/slowClock.xdc]
set_param ips.enableIPCacheLiteLoad 0
close [open __synthesis_is_running__ w]
synth_design -top slowClock -part xc7a35tcsg324-1
# disable binary constraint mode for synth run checkpoints
set_param constraints.enableBinaryConstraints false
write_checkpoint -force -noxdef slowClock.dcp
create_report "synth_1_synth_report_utilization_0" "report_utilization -file slowClock_utilization_synth.rpt -pb slowClock_utilization_synth.pb"
file delete __synthesis_is_running__
close [open __synthesis_is_complete__ w]

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Exp6-2/Exp6-2.runs/synth_1/slowClock.vds Normal file
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#-----------------------------------------------------------
# Vivado v2018.1 (64-bit)
# SW Build 2188600 on Wed Apr 4 18:40:38 MDT 2018
# IP Build 2185939 on Wed Apr 4 20:55:05 MDT 2018
# Start of session at: Thu Dec 12 20:11:37 2024
# Process ID: 23000
# Current directory: F:/Schoolwork/DigitalLogic/Exp6-2/Exp6-2.runs/synth_1
# Command line: vivado.exe -log slowClock.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source slowClock.tcl
# Log file: F:/Schoolwork/DigitalLogic/Exp6-2/Exp6-2.runs/synth_1/slowClock.vds
# Journal file: F:/Schoolwork/DigitalLogic/Exp6-2/Exp6-2.runs/synth_1\vivado.jou
#-----------------------------------------------------------
source slowClock.tcl -notrace
Command: synth_design -top slowClock -part xc7a35tcsg324-1
Starting synth_design
Attempting to get a license for feature 'Synthesis' and/or device 'xc7a35t'
INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7a35t'
INFO: Launching helper process for spawning children vivado processes
INFO: Helper process launched with PID 21660
---------------------------------------------------------------------------------
Starting RTL Elaboration : Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 409.984 ; gain = 97.137
---------------------------------------------------------------------------------
INFO: [Synth 8-6157] synthesizing module 'slowClock' [F:/Schoolwork/DigitalLogic/Exp6-2/Exp6-2.srcs/sources_1/new/slowClock.v:23]
Parameter sys_clk bound to: 100000000 - type: integer
Parameter clk_out1 bound to: 1 - type: integer
Parameter clk_out12 bound to: 12 - type: integer
Parameter clk_out48 bound to: 48 - type: integer
Parameter clk_out190 bound to: 190 - type: integer
Parameter max1 bound to: 49999999 - type: integer
Parameter max12 bound to: 4166665 - type: integer
Parameter max48 bound to: 1041665 - type: integer
Parameter max190 bound to: 263156 - type: integer
INFO: [Synth 8-6155] done synthesizing module 'slowClock' (1#1) [F:/Schoolwork/DigitalLogic/Exp6-2/Exp6-2.srcs/sources_1/new/slowClock.v:23]
---------------------------------------------------------------------------------
Finished RTL Elaboration : Time (s): cpu = 00:00:07 ; elapsed = 00:00:06 . Memory (MB): peak = 464.465 ; gain = 151.617
---------------------------------------------------------------------------------
Report Check Netlist:
+------+------------------+-------+---------+-------+------------------+
| |Item |Errors |Warnings |Status |Description |
+------+------------------+-------+---------+-------+------------------+
|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets |
+------+------------------+-------+---------+-------+------------------+
---------------------------------------------------------------------------------
Start Handling Custom Attributes
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Handling Custom Attributes : Time (s): cpu = 00:00:07 ; elapsed = 00:00:06 . Memory (MB): peak = 464.465 ; gain = 151.617
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:07 ; elapsed = 00:00:06 . Memory (MB): peak = 464.465 ; gain = 151.617
---------------------------------------------------------------------------------
INFO: [Device 21-403] Loading part xc7a35tcsg324-1
INFO: [Project 1-570] Preparing netlist for logic optimization
Processing XDC Constraints
Initializing timing engine
Parsing XDC File [F:/Schoolwork/DigitalLogic/Exp6-2/Exp6-2.srcs/constrs_1/new/slowClock.xdc]
Finished Parsing XDC File [F:/Schoolwork/DigitalLogic/Exp6-2/Exp6-2.srcs/constrs_1/new/slowClock.xdc]
INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [F:/Schoolwork/DigitalLogic/Exp6-2/Exp6-2.srcs/constrs_1/new/slowClock.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/slowClock_propImpl.xdc].
Resolution: To avoid this warning, move constraints listed in [.Xil/slowClock_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
Completed Processing XDC Constraints
INFO: [Project 1-111] Unisim Transformation Summary:
No Unisim elements were transformed.
Constraint Validation Runtime : Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 789.797 ; gain = 0.000
---------------------------------------------------------------------------------
Finished Constraint Validation : Time (s): cpu = 00:00:17 ; elapsed = 00:00:19 . Memory (MB): peak = 789.797 ; gain = 476.949
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Loading Part and Timing Information
---------------------------------------------------------------------------------
Loading part: xc7a35tcsg324-1
---------------------------------------------------------------------------------
Finished Loading Part and Timing Information : Time (s): cpu = 00:00:17 ; elapsed = 00:00:19 . Memory (MB): peak = 789.797 ; gain = 476.949
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Applying 'set_property' XDC Constraints
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:17 ; elapsed = 00:00:19 . Memory (MB): peak = 789.797 ; gain = 476.949
---------------------------------------------------------------------------------
INFO: [Synth 8-5545] ROM "clk_1Hz" won't be mapped to RAM because address size (26) is larger than maximum supported(25)
INFO: [Synth 8-5546] ROM "clk_12Hz" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "clk_48Hz" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "clk_190Hz" won't be mapped to RAM because it is too sparse
---------------------------------------------------------------------------------
Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:18 ; elapsed = 00:00:19 . Memory (MB): peak = 789.797 ; gain = 476.949
---------------------------------------------------------------------------------
Report RTL Partitions:
+-+--------------+------------+----------+
| |RTL Partition |Replication |Instances |
+-+--------------+------------+----------+
+-+--------------+------------+----------+
---------------------------------------------------------------------------------
Start RTL Component Statistics
---------------------------------------------------------------------------------
Detailed RTL Component Info :
+---Adders :
2 Input 26 Bit Adders := 1
2 Input 23 Bit Adders := 1
2 Input 21 Bit Adders := 1
2 Input 19 Bit Adders := 1
+---Registers :
26 Bit Registers := 1
23 Bit Registers := 1
21 Bit Registers := 1
19 Bit Registers := 1
1 Bit Registers := 4
+---Muxes :
2 Input 26 Bit Muxes := 1
2 Input 23 Bit Muxes := 1
2 Input 21 Bit Muxes := 1
2 Input 19 Bit Muxes := 1
2 Input 1 Bit Muxes := 4
---------------------------------------------------------------------------------
Finished RTL Component Statistics
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start RTL Hierarchical Component Statistics
---------------------------------------------------------------------------------
Hierarchical RTL Component report
Module slowClock
Detailed RTL Component Info :
+---Adders :
2 Input 26 Bit Adders := 1
2 Input 23 Bit Adders := 1
2 Input 21 Bit Adders := 1
2 Input 19 Bit Adders := 1
+---Registers :
26 Bit Registers := 1
23 Bit Registers := 1
21 Bit Registers := 1
19 Bit Registers := 1
1 Bit Registers := 4
+---Muxes :
2 Input 26 Bit Muxes := 1
2 Input 23 Bit Muxes := 1
2 Input 21 Bit Muxes := 1
2 Input 19 Bit Muxes := 1
2 Input 1 Bit Muxes := 4
---------------------------------------------------------------------------------
Finished RTL Hierarchical Component Statistics
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Part Resource Summary
---------------------------------------------------------------------------------
Part Resources:
DSPs: 90 (col length:60)
BRAMs: 100 (col length: RAMB18 60 RAMB36 30)
---------------------------------------------------------------------------------
Finished Part Resource Summary
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Cross Boundary and Area Optimization
---------------------------------------------------------------------------------
Warning: Parallel synthesis criteria is not met
INFO: [Synth 8-5545] ROM "clk_1Hz" won't be mapped to RAM because address size (26) is larger than maximum supported(25)
INFO: [Synth 8-5546] ROM "clk_12Hz" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "clk_48Hz" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "clk_190Hz" won't be mapped to RAM because it is too sparse
---------------------------------------------------------------------------------
Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:19 ; elapsed = 00:00:20 . Memory (MB): peak = 789.797 ; gain = 476.949
---------------------------------------------------------------------------------
Report RTL Partitions:
+-+--------------+------------+----------+
| |RTL Partition |Replication |Instances |
+-+--------------+------------+----------+
+-+--------------+------------+----------+
---------------------------------------------------------------------------------
Start Applying XDC Timing Constraints
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:27 ; elapsed = 00:00:29 . Memory (MB): peak = 789.797 ; gain = 476.949
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Timing Optimization
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Timing Optimization : Time (s): cpu = 00:00:27 ; elapsed = 00:00:29 . Memory (MB): peak = 789.797 ; gain = 476.949
---------------------------------------------------------------------------------
Report RTL Partitions:
+-+--------------+------------+----------+
| |RTL Partition |Replication |Instances |
+-+--------------+------------+----------+
+-+--------------+------------+----------+
---------------------------------------------------------------------------------
Start Technology Mapping
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Technology Mapping : Time (s): cpu = 00:00:27 ; elapsed = 00:00:29 . Memory (MB): peak = 797.371 ; gain = 484.523
---------------------------------------------------------------------------------
Report RTL Partitions:
+-+--------------+------------+----------+
| |RTL Partition |Replication |Instances |
+-+--------------+------------+----------+
+-+--------------+------------+----------+
---------------------------------------------------------------------------------
Start IO Insertion
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Flattening Before IO Insertion
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Flattening Before IO Insertion
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Final Netlist Cleanup
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Final Netlist Cleanup
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished IO Insertion : Time (s): cpu = 00:00:28 ; elapsed = 00:00:30 . Memory (MB): peak = 797.371 ; gain = 484.523
---------------------------------------------------------------------------------
Report Check Netlist:
+------+------------------+-------+---------+-------+------------------+
| |Item |Errors |Warnings |Status |Description |
+------+------------------+-------+---------+-------+------------------+
|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets |
+------+------------------+-------+---------+-------+------------------+
---------------------------------------------------------------------------------
Start Renaming Generated Instances
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Instances : Time (s): cpu = 00:00:28 ; elapsed = 00:00:30 . Memory (MB): peak = 797.371 ; gain = 484.523
---------------------------------------------------------------------------------
Report RTL Partitions:
+-+--------------+------------+----------+
| |RTL Partition |Replication |Instances |
+-+--------------+------------+----------+
+-+--------------+------------+----------+
---------------------------------------------------------------------------------
Start Rebuilding User Hierarchy
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:28 ; elapsed = 00:00:30 . Memory (MB): peak = 797.371 ; gain = 484.523
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Ports
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Ports : Time (s): cpu = 00:00:28 ; elapsed = 00:00:30 . Memory (MB): peak = 797.371 ; gain = 484.523
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Handling Custom Attributes
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Handling Custom Attributes : Time (s): cpu = 00:00:28 ; elapsed = 00:00:30 . Memory (MB): peak = 797.371 ; gain = 484.523
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Nets
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Nets : Time (s): cpu = 00:00:28 ; elapsed = 00:00:30 . Memory (MB): peak = 797.371 ; gain = 484.523
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Writing Synthesis Report
---------------------------------------------------------------------------------
Report BlackBoxes:
+-+--------------+----------+
| |BlackBox name |Instances |
+-+--------------+----------+
+-+--------------+----------+
Report Cell Usage:
+------+-------+------+
| |Cell |Count |
+------+-------+------+
|1 |BUFG | 1|
|2 |CARRY4 | 23|
|3 |LUT1 | 3|
|4 |LUT2 | 49|
|5 |LUT3 | 1|
|6 |LUT4 | 17|
|7 |LUT5 | 2|
|8 |LUT6 | 44|
|9 |FDCE | 93|
|10 |IBUF | 2|
|11 |OBUF | 4|
+------+-------+------+
Report Instance Areas:
+------+---------+-------+------+
| |Instance |Module |Cells |
+------+---------+-------+------+
|1 |top | | 239|
+------+---------+-------+------+
---------------------------------------------------------------------------------
Finished Writing Synthesis Report : Time (s): cpu = 00:00:28 ; elapsed = 00:00:30 . Memory (MB): peak = 797.371 ; gain = 484.523
---------------------------------------------------------------------------------
Synthesis finished with 0 errors, 0 critical warnings and 0 warnings.
Synthesis Optimization Runtime : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 797.371 ; gain = 159.191
Synthesis Optimization Complete : Time (s): cpu = 00:00:28 ; elapsed = 00:00:30 . Memory (MB): peak = 797.371 ; gain = 484.523
INFO: [Project 1-571] Translating synthesized netlist
INFO: [Netlist 29-17] Analyzing 25 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
INFO: [Project 1-570] Preparing netlist for logic optimization
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
INFO: [Project 1-111] Unisim Transformation Summary:
No Unisim elements were transformed.
INFO: [Common 17-83] Releasing license: Synthesis
22 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
synth_design completed successfully
synth_design: Time (s): cpu = 00:00:28 ; elapsed = 00:00:33 . Memory (MB): peak = 805.500 ; gain = 505.727
INFO: [Common 17-1381] The checkpoint 'F:/Schoolwork/DigitalLogic/Exp6-2/Exp6-2.runs/synth_1/slowClock.dcp' has been generated.
INFO: [runtcl-4] Executing : report_utilization -file slowClock_utilization_synth.rpt -pb slowClock_utilization_synth.pb
report_utilization: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.022 . Memory (MB): peak = 805.500 ; gain = 0.000
INFO: [Common 17-206] Exiting Vivado at Thu Dec 12 20:12:13 2024...

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Exp6-2/Exp6-2.runs/synth_1/slowClock_utilization_synth.pb Normal file
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Exp6-2/Exp6-2.runs/synth_1/slowClock_utilization_synth.rpt Normal file
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Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
-------------------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2018.1 (win64) Build 2188600 Wed Apr 4 18:40:38 MDT 2018
| Date : Thu Dec 12 20:12:13 2024
| Host : W10-20240912132 running 64-bit major release (build 9200)
| Command : report_utilization -file slowClock_utilization_synth.rpt -pb slowClock_utilization_synth.pb
| Design : slowClock
| Device : 7a35tcsg324-1
| Design State : Synthesized
-------------------------------------------------------------------------------------------------------------
Utilization Design Information
Table of Contents
-----------------
1. Slice Logic
1.1 Summary of Registers by Type
2. Memory
3. DSP
4. IO and GT Specific
5. Clocking
6. Specific Feature
7. Primitives
8. Black Boxes
9. Instantiated Netlists
1. Slice Logic
--------------
+-------------------------+------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+-------------------------+------+-------+-----------+-------+
| Slice LUTs* | 90 | 0 | 20800 | 0.43 |
| LUT as Logic | 90 | 0 | 20800 | 0.43 |
| LUT as Memory | 0 | 0 | 9600 | 0.00 |
| Slice Registers | 93 | 0 | 41600 | 0.22 |
| Register as Flip Flop | 93 | 0 | 41600 | 0.22 |
| Register as Latch | 0 | 0 | 41600 | 0.00 |
| F7 Muxes | 0 | 0 | 16300 | 0.00 |
| F8 Muxes | 0 | 0 | 8150 | 0.00 |
+-------------------------+------+-------+-----------+-------+
* Warning! The Final LUT count, after physical optimizations and full implementation, is typically lower. Run opt_design after synthesis, if not already completed, for a more realistic count.
1.1 Summary of Registers by Type
--------------------------------
+-------+--------------+-------------+--------------+
| Total | Clock Enable | Synchronous | Asynchronous |
+-------+--------------+-------------+--------------+
| 0 | _ | - | - |
| 0 | _ | - | Set |
| 0 | _ | - | Reset |
| 0 | _ | Set | - |
| 0 | _ | Reset | - |
| 0 | Yes | - | - |
| 0 | Yes | - | Set |
| 93 | Yes | - | Reset |
| 0 | Yes | Set | - |
| 0 | Yes | Reset | - |
+-------+--------------+-------------+--------------+
2. Memory
---------
+----------------+------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+----------------+------+-------+-----------+-------+
| Block RAM Tile | 0 | 0 | 50 | 0.00 |
| RAMB36/FIFO* | 0 | 0 | 50 | 0.00 |
| RAMB18 | 0 | 0 | 100 | 0.00 |
+----------------+------+-------+-----------+-------+
* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1
3. DSP
------
+-----------+------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+-----------+------+-------+-----------+-------+
| DSPs | 0 | 0 | 90 | 0.00 |
+-----------+------+-------+-----------+-------+
4. IO and GT Specific
---------------------
+-----------------------------+------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+-----------------------------+------+-------+-----------+-------+
| Bonded IOB | 6 | 0 | 210 | 2.86 |
| Bonded IPADs | 0 | 0 | 2 | 0.00 |
| PHY_CONTROL | 0 | 0 | 5 | 0.00 |
| PHASER_REF | 0 | 0 | 5 | 0.00 |
| OUT_FIFO | 0 | 0 | 20 | 0.00 |
| IN_FIFO | 0 | 0 | 20 | 0.00 |
| IDELAYCTRL | 0 | 0 | 5 | 0.00 |
| IBUFDS | 0 | 0 | 202 | 0.00 |
| PHASER_OUT/PHASER_OUT_PHY | 0 | 0 | 20 | 0.00 |
| PHASER_IN/PHASER_IN_PHY | 0 | 0 | 20 | 0.00 |
| IDELAYE2/IDELAYE2_FINEDELAY | 0 | 0 | 250 | 0.00 |
| ILOGIC | 0 | 0 | 210 | 0.00 |
| OLOGIC | 0 | 0 | 210 | 0.00 |
+-----------------------------+------+-------+-----------+-------+
5. Clocking
-----------
+------------+------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+------------+------+-------+-----------+-------+
| BUFGCTRL | 1 | 0 | 32 | 3.13 |
| BUFIO | 0 | 0 | 20 | 0.00 |
| MMCME2_ADV | 0 | 0 | 5 | 0.00 |
| PLLE2_ADV | 0 | 0 | 5 | 0.00 |
| BUFMRCE | 0 | 0 | 10 | 0.00 |
| BUFHCE | 0 | 0 | 72 | 0.00 |
| BUFR | 0 | 0 | 20 | 0.00 |
+------------+------+-------+-----------+-------+
6. Specific Feature
-------------------
+-------------+------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+-------------+------+-------+-----------+-------+
| BSCANE2 | 0 | 0 | 4 | 0.00 |
| CAPTUREE2 | 0 | 0 | 1 | 0.00 |
| DNA_PORT | 0 | 0 | 1 | 0.00 |
| EFUSE_USR | 0 | 0 | 1 | 0.00 |
| FRAME_ECCE2 | 0 | 0 | 1 | 0.00 |
| ICAPE2 | 0 | 0 | 2 | 0.00 |
| PCIE_2_1 | 0 | 0 | 1 | 0.00 |
| STARTUPE2 | 0 | 0 | 1 | 0.00 |
| XADC | 0 | 0 | 1 | 0.00 |
+-------------+------+-------+-----------+-------+
7. Primitives
-------------
+----------+------+---------------------+
| Ref Name | Used | Functional Category |
+----------+------+---------------------+
| FDCE | 93 | Flop & Latch |
| LUT2 | 49 | LUT |
| LUT6 | 44 | LUT |
| CARRY4 | 23 | CarryLogic |
| LUT4 | 17 | LUT |
| OBUF | 4 | IO |
| LUT1 | 3 | LUT |
| LUT5 | 2 | LUT |
| IBUF | 2 | IO |
| LUT3 | 1 | LUT |
| BUFG | 1 | Clock |
+----------+------+---------------------+
8. Black Boxes
--------------
+----------+------+
| Ref Name | Used |
+----------+------+
9. Instantiated Netlists
------------------------
+----------+------+
| Ref Name | Used |
+----------+------+

12
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#-----------------------------------------------------------
# Vivado v2018.1 (64-bit)
# SW Build 2188600 on Wed Apr 4 18:40:38 MDT 2018
# IP Build 2185939 on Wed Apr 4 20:55:05 MDT 2018
# Start of session at: Thu Dec 12 20:11:37 2024
# Process ID: 23000
# Current directory: F:/Schoolwork/DigitalLogic/Exp6-2/Exp6-2.runs/synth_1
# Command line: vivado.exe -log slowClock.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source slowClock.tcl
# Log file: F:/Schoolwork/DigitalLogic/Exp6-2/Exp6-2.runs/synth_1/slowClock.vds
# Journal file: F:/Schoolwork/DigitalLogic/Exp6-2/Exp6-2.runs/synth_1\vivado.jou
#-----------------------------------------------------------
source slowClock.tcl -notrace

BIN
Exp6-2/Exp6-2.runs/synth_1/vivado.pb Normal file
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