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2025-11-06 10:08:01 +08:00
commit 0bded5b86e
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71
Exp6-2/Exp6-2.sim/sim_1/behav/xsim/glbl.v Normal file
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// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (strong1, weak0) GSR = GSR_int;
assign (strong1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif

11
Exp6-2/Exp6-2.sim/sim_1/behav/xsim/tb_slowClock.tcl Normal file
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set curr_wave [current_wave_config]
if { [string length $curr_wave] == 0 } {
if { [llength [get_objects]] > 0} {
add_wave /
set_property needs_save false [current_wave_config]
} else {
send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
}
}
run 1000ns

10
Exp6-2/Exp6-2.sim/sim_1/behav/xsim/tb_slowClock_vlog.prj Normal file
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# compile verilog/system verilog design source files
verilog xil_defaultlib \
"../../../../Exp6-2.srcs/sources_1/new/slowClock.v" \
"../../../../Exp6-2.srcs/sim_1/new/tb_slowClock.v" \
# compile glbl module
verilog xil_defaultlib "glbl.v"
# Do not sort compile order
nosort

12
Exp6-2/Exp6-2.sim/sim_1/behav/xsim/webtalk.jou Normal file
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#-----------------------------------------------------------
# Webtalk v2018.1 (64-bit)
# SW Build 2188600 on Wed Apr 4 18:40:38 MDT 2018
# IP Build 2185939 on Wed Apr 4 20:55:05 MDT 2018
# Start of session at: Thu Dec 12 11:34:13 2024
# Process ID: 70688
# Current directory: F:/Schoolwork/DigitalLogic/Exp6-2/Exp6-2.sim/sim_1/behav/xsim
# Command line: wbtcv.exe -mode batch -source F:/Schoolwork/DigitalLogic/Exp6-2/Exp6-2.sim/sim_1/behav/xsim/xsim.dir/tb_slowClock_behav/webtalk/xsim_webtalk.tcl -notrace
# Log file: F:/Schoolwork/DigitalLogic/Exp6-2/Exp6-2.sim/sim_1/behav/xsim/webtalk.log
# Journal file: F:/Schoolwork/DigitalLogic/Exp6-2/Exp6-2.sim/sim_1/behav/xsim\webtalk.jou
#-----------------------------------------------------------
source F:/Schoolwork/DigitalLogic/Exp6-2/Exp6-2.sim/sim_1/behav/xsim/xsim.dir/tb_slowClock_behav/webtalk/xsim_webtalk.tcl -notrace

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Exp6-2/Exp6-2.sim/sim_1/behav/xsim/webtalk_11576.backup.jou Normal file
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#-----------------------------------------------------------
# Webtalk v2018.1 (64-bit)
# SW Build 2188600 on Wed Apr 4 18:40:38 MDT 2018
# IP Build 2185939 on Wed Apr 4 20:55:05 MDT 2018
# Start of session at: Wed Dec 4 22:56:01 2024
# Process ID: 11576
# Current directory: F:/Schoolwork/DigitalLogic/Exp6-2/Exp6-2.sim/sim_1/behav/xsim
# Command line: wbtcv.exe -mode batch -source F:/Schoolwork/DigitalLogic/Exp6-2/Exp6-2.sim/sim_1/behav/xsim/xsim.dir/tb_slowClock_behav/webtalk/xsim_webtalk.tcl -notrace
# Log file: F:/Schoolwork/DigitalLogic/Exp6-2/Exp6-2.sim/sim_1/behav/xsim/webtalk.log
# Journal file: F:/Schoolwork/DigitalLogic/Exp6-2/Exp6-2.sim/sim_1/behav/xsim\webtalk.jou
#-----------------------------------------------------------
source F:/Schoolwork/DigitalLogic/Exp6-2/Exp6-2.sim/sim_1/behav/xsim/xsim.dir/tb_slowClock_behav/webtalk/xsim_webtalk.tcl -notrace

12
Exp6-2/Exp6-2.sim/sim_1/behav/xsim/webtalk_30300.backup.jou Normal file
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#-----------------------------------------------------------
# Webtalk v2018.1 (64-bit)
# SW Build 2188600 on Wed Apr 4 18:40:38 MDT 2018
# IP Build 2185939 on Wed Apr 4 20:55:05 MDT 2018
# Start of session at: Thu Dec 5 10:20:54 2024
# Process ID: 30300
# Current directory: F:/Schoolwork/DigitalLogic/Exp6-2/Exp6-2.sim/sim_1/behav/xsim
# Command line: wbtcv.exe -mode batch -source F:/Schoolwork/DigitalLogic/Exp6-2/Exp6-2.sim/sim_1/behav/xsim/xsim.dir/tb_slowClock_behav/webtalk/xsim_webtalk.tcl -notrace
# Log file: F:/Schoolwork/DigitalLogic/Exp6-2/Exp6-2.sim/sim_1/behav/xsim/webtalk.log
# Journal file: F:/Schoolwork/DigitalLogic/Exp6-2/Exp6-2.sim/sim_1/behav/xsim\webtalk.jou
#-----------------------------------------------------------
source F:/Schoolwork/DigitalLogic/Exp6-2/Exp6-2.sim/sim_1/behav/xsim/xsim.dir/tb_slowClock_behav/webtalk/xsim_webtalk.tcl -notrace

12
Exp6-2/Exp6-2.sim/sim_1/behav/xsim/webtalk_37912.backup.jou Normal file
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#-----------------------------------------------------------
# Webtalk v2018.1 (64-bit)
# SW Build 2188600 on Wed Apr 4 18:40:38 MDT 2018
# IP Build 2185939 on Wed Apr 4 20:55:05 MDT 2018
# Start of session at: Thu Dec 12 11:33:54 2024
# Process ID: 37912
# Current directory: F:/Schoolwork/DigitalLogic/Exp6-2/Exp6-2.sim/sim_1/behav/xsim
# Command line: wbtcv.exe -mode batch -source F:/Schoolwork/DigitalLogic/Exp6-2/Exp6-2.sim/sim_1/behav/xsim/xsim.dir/tb_slowClock_behav/webtalk/xsim_webtalk.tcl -notrace
# Log file: F:/Schoolwork/DigitalLogic/Exp6-2/Exp6-2.sim/sim_1/behav/xsim/webtalk.log
# Journal file: F:/Schoolwork/DigitalLogic/Exp6-2/Exp6-2.sim/sim_1/behav/xsim\webtalk.jou
#-----------------------------------------------------------
source F:/Schoolwork/DigitalLogic/Exp6-2/Exp6-2.sim/sim_1/behav/xsim/xsim.dir/tb_slowClock_behav/webtalk/xsim_webtalk.tcl -notrace

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Exp6-2/Exp6-2.sim/sim_1/behav/xsim/xelab.pb Normal file
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Exp6-2/Exp6-2.sim/sim_1/behav/xsim/xsim.dir/tb_slowClock_behav/Compile_Options.txt Normal file
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-wto "4300d764479b496ebf4784ba09aabf1f" --incr --debug "typical" --relax --mt "2" -L "xil_defaultlib" -L "unisims_ver" -L "unimacro_ver" -L "secureip" --snapshot "tb_slowClock_behav" "xil_defaultlib.tb_slowClock" "xil_defaultlib.glbl" -log "elaborate.log"

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Exp6-2/Exp6-2.sim/sim_1/behav/xsim/xsim.dir/tb_slowClock_behav/TempBreakPointFile.txt Normal file
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Breakpoint File Version 1.0

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Exp6-2/Exp6-2.sim/sim_1/behav/xsim/xsim.dir/tb_slowClock_behav/obj/xsim_1.c Normal file
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/**********************************************************************/
/* ____ ____ */
/* / /\/ / */
/* /___/ \ / */
/* \ \ \/ */
/* \ \ Copyright (c) 2003-2013 Xilinx, Inc. */
/* / / All Right Reserved. */
/* /---/ /\ */
/* \ \ / \ */
/* \___\/\___\ */
/**********************************************************************/
#include "iki.h"
#include <string.h>
#include <math.h>
#ifdef __GNUC__
#include <stdlib.h>
#else
#include <malloc.h>
#define alloca _alloca
#endif
/**********************************************************************/
/* ____ ____ */
/* / /\/ / */
/* /___/ \ / */
/* \ \ \/ */
/* \ \ Copyright (c) 2003-2013 Xilinx, Inc. */
/* / / All Right Reserved. */
/* /---/ /\ */
/* \ \ / \ */
/* \___\/\___\ */
/**********************************************************************/
#include "iki.h"
#include <string.h>
#include <math.h>
#ifdef __GNUC__
#include <stdlib.h>
#else
#include <malloc.h>
#define alloca _alloca
#endif
typedef void (*funcp)(char *, char *);
extern int main(int, char**);
extern void execute_4(char*, char *);
extern void execute_5(char*, char *);
extern void execute_6(char*, char *);
extern void execute_11(char*, char *);
extern void execute_12(char*, char *);
extern void execute_13(char*, char *);
extern void execute_14(char*, char *);
extern void execute_15(char*, char *);
extern void execute_16(char*, char *);
extern void execute_3(char*, char *);
extern void execute_8(char*, char *);
extern void execute_9(char*, char *);
extern void execute_10(char*, char *);
extern void execute_17(char*, char *);
extern void execute_18(char*, char *);
extern void execute_19(char*, char *);
extern void execute_20(char*, char *);
extern void execute_21(char*, char *);
extern void vlog_transfunc_eventcallback(char*, char*, unsigned, unsigned, unsigned, char *);
funcp funcTab[19] = {(funcp)execute_4, (funcp)execute_5, (funcp)execute_6, (funcp)execute_11, (funcp)execute_12, (funcp)execute_13, (funcp)execute_14, (funcp)execute_15, (funcp)execute_16, (funcp)execute_3, (funcp)execute_8, (funcp)execute_9, (funcp)execute_10, (funcp)execute_17, (funcp)execute_18, (funcp)execute_19, (funcp)execute_20, (funcp)execute_21, (funcp)vlog_transfunc_eventcallback};
const int NumRelocateId= 19;
void relocate(char *dp)
{
iki_relocate(dp, "xsim.dir/tb_slowClock_behav/xsim.reloc", (void **)funcTab, 19);
/*Populate the transaction function pointer field in the whole net structure */
}
void sensitize(char *dp)
{
iki_sensitize(dp, "xsim.dir/tb_slowClock_behav/xsim.reloc");
}
void simulate(char *dp)
{
iki_schedule_processes_at_time_zero(dp, "xsim.dir/tb_slowClock_behav/xsim.reloc");
// Initialize Verilog nets in mixed simulation, for the cases when the value at time 0 should be propagated from the mixed language Vhdl net
iki_execute_processes();
// Schedule resolution functions for the multiply driven Verilog nets that have strength
// Schedule transaction functions for the singly driven Verilog nets that have strength
}
#include "iki_bridge.h"
void relocate(char *);
void sensitize(char *);
void simulate(char *);
extern SYSTEMCLIB_IMP_DLLSPEC void local_register_implicit_channel(int, char*);
extern void implicit_HDL_SCinstatiate();
extern int xsim_argc_copy ;
extern char** xsim_argv_copy ;
int main(int argc, char **argv)
{
iki_heap_initialize("ms", "isimmm", 0, 2147483648) ;
iki_set_sv_type_file_path_name("xsim.dir/tb_slowClock_behav/xsim.svtype");
iki_set_crvs_dump_file_path_name("xsim.dir/tb_slowClock_behav/xsim.crvsdump");
void* design_handle = iki_create_design("xsim.dir/tb_slowClock_behav/xsim.mem", (void *)relocate, (void *)sensitize, (void *)simulate, 0, isimBridge_getWdbWriter(), 0, argc, argv);
iki_set_rc_trial_count(100);
(void) design_handle;
return iki_simulate_design();
}

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Exp6-2/Exp6-2.sim/sim_1/behav/xsim/xsim.dir/tb_slowClock_behav/webtalk/xsim_webtalk.tcl Normal file
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webtalk_init -webtalk_dir F:/Schoolwork/DigitalLogic/Exp6-2/Exp6-2.sim/sim_1/behav/xsim/xsim.dir/tb_slowClock_behav/webtalk/
webtalk_register_client -client project
webtalk_add_data -client project -key date_generated -value "Thu Dec 12 14:36:26 2024" -context "software_version_and_target_device"
webtalk_add_data -client project -key product_version -value "XSIM v2018.1 (64-bit)" -context "software_version_and_target_device"
webtalk_add_data -client project -key build_version -value "2188600" -context "software_version_and_target_device"
webtalk_add_data -client project -key os_platform -value "WIN64" -context "software_version_and_target_device"
webtalk_add_data -client project -key registration_id -value "" -context "software_version_and_target_device"
webtalk_add_data -client project -key tool_flow -value "xsim_vivado" -context "software_version_and_target_device"
webtalk_add_data -client project -key beta -value "FALSE" -context "software_version_and_target_device"
webtalk_add_data -client project -key route_design -value "FALSE" -context "software_version_and_target_device"
webtalk_add_data -client project -key target_family -value "not_applicable" -context "software_version_and_target_device"
webtalk_add_data -client project -key target_device -value "not_applicable" -context "software_version_and_target_device"
webtalk_add_data -client project -key target_package -value "not_applicable" -context "software_version_and_target_device"
webtalk_add_data -client project -key target_speed -value "not_applicable" -context "software_version_and_target_device"
webtalk_add_data -client project -key random_id -value "78ec1a93-fd1a-4b14-8c4b-87f04256706b" -context "software_version_and_target_device"
webtalk_add_data -client project -key project_id -value "4300d764479b496ebf4784ba09aabf1f" -context "software_version_and_target_device"
webtalk_add_data -client project -key project_iteration -value "10" -context "software_version_and_target_device"
webtalk_add_data -client project -key os_name -value "Microsoft Windows 8 or later , 64-bit" -context "user_environment"
webtalk_add_data -client project -key os_release -value "major release (build 9200)" -context "user_environment"
webtalk_add_data -client project -key cpu_name -value "13th Gen Intel(R) Core(TM) i7-13700H" -context "user_environment"
webtalk_add_data -client project -key cpu_speed -value "2918 MHz" -context "user_environment"
webtalk_add_data -client project -key total_processors -value "1" -context "user_environment"
webtalk_add_data -client project -key system_ram -value "16.000 GB" -context "user_environment"
webtalk_register_client -client xsim
webtalk_add_data -client xsim -key Command -value "xsim" -context "xsim\\command_line_options"
webtalk_add_data -client xsim -key trace_waveform -value "true" -context "xsim\\usage"
webtalk_add_data -client xsim -key runtime -value "1 us" -context "xsim\\usage"
webtalk_add_data -client xsim -key iteration -value "1" -context "xsim\\usage"
webtalk_add_data -client xsim -key Simulation_Time -value "0.08_sec" -context "xsim\\usage"
webtalk_add_data -client xsim -key Simulation_Memory -value "6672_KB" -context "xsim\\usage"
webtalk_transmit -clientid 2415603722 -regid "" -xml F:/Schoolwork/DigitalLogic/Exp6-2/Exp6-2.sim/sim_1/behav/xsim/xsim.dir/tb_slowClock_behav/webtalk/usage_statistics_ext_xsim.xml -html F:/Schoolwork/DigitalLogic/Exp6-2/Exp6-2.sim/sim_1/behav/xsim/xsim.dir/tb_slowClock_behav/webtalk/usage_statistics_ext_xsim.html -wdm F:/Schoolwork/DigitalLogic/Exp6-2/Exp6-2.sim/sim_1/behav/xsim/xsim.dir/tb_slowClock_behav/webtalk/usage_statistics_ext_xsim.wdm -intro "<H3>XSIM Usage Report</H3><BR>"
webtalk_terminate

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