Initial commit

Exp6-2/Exp6-2.srcs/sim_1/new/tb_slowClock.v

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+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date: 2024/12/04 22:55:01
+// Design Name: 
+// Module Name: tb_slowClock
+// Project Name: 
+// Target Devices: 
+// Tool Versions: 
+// Description: 
+// 
+// Dependencies: 
+// 
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+// 
+//////////////////////////////////////////////////////////////////////////////////
+
+
+module tb_slowClock;
+    reg clk;
+    reg reset;
+    wire clk_1Hz;
+    wire clk_12Hz;
+    wire clk_48Hz;
+    wire clk_190Hz;
+    slowClock uut (
+        .clk(clk),
+        .reset(reset),
+        .clk_1Hz(clk_1Hz),
+        .clk_12Hz(clk_12Hz),
+        .clk_48Hz(clk_48Hz),
+        .clk_190Hz(clk_190Hz)
+    );
+    initial begin
+        clk = 0;
+        forever #1 clk = ~clk;
+    end
+    initial begin
+        reset = 1;
+        #20;
+        reset = 0;
+    end
+    initial begin
+        #1000000000;
+        $finish;
+    end
+endmodule