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2025-11-06 10:08:01 +08:00
commit 0bded5b86e
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40
Exp7/Exp7.srcs/constrs_1/new/led_chasing.xdc Normal file
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set_property IOSTANDARD LVCMOS33 [get_ports {led[15]}]
set_property IOSTANDARD LVCMOS33 [get_ports {led[14]}]
set_property IOSTANDARD LVCMOS33 [get_ports {led[13]}]
set_property IOSTANDARD LVCMOS33 [get_ports {led[12]}]
set_property IOSTANDARD LVCMOS33 [get_ports {led[11]}]
set_property IOSTANDARD LVCMOS33 [get_ports {led[10]}]
set_property IOSTANDARD LVCMOS33 [get_ports {led[9]}]
set_property IOSTANDARD LVCMOS33 [get_ports {led[8]}]
set_property IOSTANDARD LVCMOS33 [get_ports {led[7]}]
set_property IOSTANDARD LVCMOS33 [get_ports {led[6]}]
set_property IOSTANDARD LVCMOS33 [get_ports {led[5]}]
set_property IOSTANDARD LVCMOS33 [get_ports {led[4]}]
set_property IOSTANDARD LVCMOS33 [get_ports {led[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {led[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {led[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {led[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports clk]
set_property IOSTANDARD LVCMOS33 [get_ports direction_ctrl]
set_property IOSTANDARD LVCMOS33 [get_ports reset]
set_property IOSTANDARD LVCMOS33 [get_ports speed_ctrl]
set_property PACKAGE_PIN P17 [get_ports clk]
set_property PACKAGE_PIN F6 [get_ports {led[15]}]
set_property PACKAGE_PIN G4 [get_ports {led[14]}]
set_property PACKAGE_PIN G3 [get_ports {led[13]}]
set_property PACKAGE_PIN J4 [get_ports {led[12]}]
set_property PACKAGE_PIN H4 [get_ports {led[11]}]
set_property PACKAGE_PIN J3 [get_ports {led[10]}]
set_property PACKAGE_PIN J2 [get_ports {led[9]}]
set_property PACKAGE_PIN K2 [get_ports {led[8]}]
set_property PACKAGE_PIN K1 [get_ports {led[7]}]
set_property PACKAGE_PIN H6 [get_ports {led[6]}]
set_property PACKAGE_PIN H5 [get_ports {led[5]}]
set_property PACKAGE_PIN J5 [get_ports {led[4]}]
set_property PACKAGE_PIN K6 [get_ports {led[3]}]
set_property PACKAGE_PIN L1 [get_ports {led[2]}]
set_property PACKAGE_PIN M1 [get_ports {led[1]}]
set_property PACKAGE_PIN K3 [get_ports {led[0]}]
set_property PACKAGE_PIN P4 [get_ports direction_ctrl]
set_property PACKAGE_PIN R1 [get_ports reset]
set_property PACKAGE_PIN P5 [get_ports speed_ctrl]

54
Exp7/Exp7.srcs/sim_1/new/led_chasing_tb.v Normal file
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`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2024/12/12 10:11:33
// Design Name:
// Module Name: led_chasing_tb
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module led_chasing_tb();
reg clk;
reg reset;
reg speed_ctrl;
reg direction_ctrl;
wire [15:0] led;
led_chasing dut(
.clk(clk),
.reset(reset),
.speed_ctrl(speed_ctrl),
.direction_ctrl(direction_ctrl),
.led(led)
);
initial begin
clk = 0;
forever #1 clk = ~clk;
end
initial begin
reset = 1;
speed_ctrl = 0;
direction_ctrl = 0;
#100 reset = 0;
#1000;
speed_ctrl = 1;
#1000;
direction_ctrl = 1;
#1000;
speed_ctrl = 0;
#1000;
$finish;
end
endmodule

29
Exp7/Exp7.srcs/sources_1/new/led_chasing.v Normal file
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`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2024/12/05 11:15:53
// Design Name:
// Module Name: led_chasing
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module led_chasing(clk, reset, speed_ctrl, direction_ctrl, led);
input clk, reset, speed_ctrl, direction_ctrl;
output [15:0] led;
wire clk_out;
slow_clock getclock (.clk(clk), .reset(reset), .speed_ctrl(speed_ctrl), .clk_out(clk_out));
shift_reg run (.reset(reset), .clk(clk_out), .direction_ctrl(direction_ctrl), .cnt(led));
endmodule

37
Exp7/Exp7.srcs/sources_1/new/shift_reg.v Normal file
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`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2024/12/05 11:33:38
// Design Name:
// Module Name: shift_reg
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module shift_reg(reset, clk, direction_ctrl, cnt);
parameter CNT_SIZE = 16;
input reset, clk, direction_ctrl;
output reg [CNT_SIZE-1 : 0] cnt;
always @(posedge clk or posedge reset) begin
if (reset)
cnt <= 16'b0000000000000001;
else begin
if (direction_ctrl == 0)
cnt <= {cnt[0], cnt[CNT_SIZE-1 : 1]};
else
cnt <= {cnt[CNT_SIZE-2 : 0], cnt[CNT_SIZE-1]};
end
end
endmodule

60
Exp7/Exp7.srcs/sources_1/new/slow_clock.v Normal file
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`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2024/12/05 11:21:41
// Design Name:
// Module Name: slow_clock
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module slow_clock(clk, reset, speed_ctrl, clk_out);
input clk, reset, speed_ctrl;
output reg clk_out;
parameter sys_clk = 100_000_000;
parameter clk_slow = 1;
parameter clk_fast = 5;
parameter max_slow = sys_clk / (2 * clk_slow) - 1;
// parameter max_slow = 10 - 1; // for simulation
parameter max_fast = sys_clk / (2 * clk_fast) - 1;
// parameter max_fast = 5 - 1; // for simulation
reg [25:0] counter;
always @(posedge clk or posedge reset) begin
if (reset) begin
counter <= 0;
clk_out <= 0;
end
else begin
if (speed_ctrl == 0) begin
if (counter == max_slow) begin
counter <= 0;
clk_out <= ~clk_out;
end
else begin
counter <= counter + 1;
end
end
else if (speed_ctrl == 1) begin
if (counter == max_fast) begin
counter <= 0;
clk_out <= ~clk_out;
end
else begin
counter <= counter + 1;
end
end
end
end
endmodule