Initial commit

Exp7/Exp7.srcs/sources_1/new/led_chasing.v

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+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date: 2024/12/05 11:15:53
+// Design Name: 
+// Module Name: led_chasing
+// Project Name: 
+// Target Devices: 
+// Tool Versions: 
+// Description: 
+// 
+// Dependencies: 
+// 
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+// 
+//////////////////////////////////////////////////////////////////////////////////
+
+
+module led_chasing(clk, reset, speed_ctrl, direction_ctrl, led);
+input clk, reset, speed_ctrl, direction_ctrl;
+output [15:0] led;
+wire clk_out;
+slow_clock getclock (.clk(clk), .reset(reset), .speed_ctrl(speed_ctrl), .clk_out(clk_out));
+shift_reg run (.reset(reset), .clk(clk_out), .direction_ctrl(direction_ctrl), .cnt(led));
+endmodule

Exp7/Exp7.srcs/sources_1/new/shift_reg.v

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+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date: 2024/12/05 11:33:38
+// Design Name: 
+// Module Name: shift_reg
+// Project Name: 
+// Target Devices: 
+// Tool Versions: 
+// Description: 
+// 
+// Dependencies: 
+// 
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+// 
+//////////////////////////////////////////////////////////////////////////////////
+
+
+module shift_reg(reset, clk, direction_ctrl, cnt);
+parameter CNT_SIZE = 16;
+input reset, clk, direction_ctrl;
+output reg [CNT_SIZE-1 : 0] cnt;
+always @(posedge clk or posedge reset) begin
+    if (reset)
+    cnt <= 16'b0000000000000001;
+    else begin
+        if (direction_ctrl == 0)
+            cnt <= {cnt[0], cnt[CNT_SIZE-1 : 1]};
+        else
+            cnt <= {cnt[CNT_SIZE-2 : 0], cnt[CNT_SIZE-1]};
+    end
+end
+endmodule

Exp7/Exp7.srcs/sources_1/new/slow_clock.v

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+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date: 2024/12/05 11:21:41
+// Design Name: 
+// Module Name: slow_clock
+// Project Name: 
+// Target Devices: 
+// Tool Versions: 
+// Description: 
+// 
+// Dependencies: 
+// 
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+// 
+//////////////////////////////////////////////////////////////////////////////////
+
+
+module slow_clock(clk, reset, speed_ctrl, clk_out);
+    input clk, reset, speed_ctrl;
+    output reg clk_out;
+    parameter sys_clk = 100_000_000;
+    parameter clk_slow = 1;
+    parameter clk_fast = 5;
+    parameter max_slow = sys_clk / (2 * clk_slow) - 1;
+//  parameter max_slow = 10 - 1; // for simulation
+    parameter max_fast = sys_clk / (2 * clk_fast) - 1;
+//  parameter max_fast = 5 - 1; // for simulation
+    reg [25:0] counter;
+    always @(posedge clk or posedge reset) begin
+        if (reset) begin
+            counter <= 0;
+            clk_out <= 0;
+        end
+        else begin
+            if (speed_ctrl == 0) begin
+                if (counter == max_slow) begin
+                    counter <= 0;
+                    clk_out <= ~clk_out;
+                end
+                else begin
+                    counter <= counter + 1;
+                end
+            end
+            else if (speed_ctrl == 1) begin
+                if (counter == max_fast) begin
+                    counter <= 0;
+                    clk_out <= ~clk_out;
+                end
+                else begin
+                    counter <= counter + 1;
+                end
+            end
+        end
+    end
+endmodule