Initial commit

Exp8-1/Exp8-1.srcs/sim_1/new/tb_sequence_detector_11001.v

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+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date: 2024/12/12 01:59:18
+// Design Name: 
+// Module Name: tb_sequence_detector_11001
+// Project Name: 
+// Target Devices: 
+// Tool Versions: 
+// Description: 
+// 
+// Dependencies: 
+// 
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+// 
+//////////////////////////////////////////////////////////////////////////////////
+
+
+module tb_sequence_detector_11001();
+reg clk;
+reg reset;
+reg x;
+wire z;
+sequence_detector_11001 uut (
+    .clk(clk),
+    .reset(reset),
+    .x(x),
+    .z(z)
+);
+always #5 clk = ~clk;
+initial begin
+    // Init signal
+    clk = 0;
+    reset = 1;
+    x = 0;
+    // Undo reset
+    #10 reset = 0;
+    // Test sequences
+    #10 x = 1;  // S0 -> S1
+    #10 x = 1;  // S1 -> S2
+    #10 x = 0;  // S2 -> S3
+    #10 x = 0;  // S3 -> S4
+    #10 x = 1;  // S4 -> S5 (11001)
+    // Reset
+    #10 reset = 1;
+    #10 reset = 0;
+    // Test multiple sequences
+    #10 x = 1;  // S0 -> S1
+    #10 x = 1;  // S1 -> S2
+    #10 x = 0;  // S2 -> S3
+    #10 x = 0;  // S3 -> S4
+    #10 x = 1;  // S4 -> S5 (11001)
+    #10 x = 0;  // No operation
+    #10 x = 1;  // S0 -> S1
+    #20 $finish;
+end
+endmodule