Initial commit
This commit is contained in:
57
Exp8-2/Exp8-2.cache/wt/webtalk_pa.xml
Normal file
57
Exp8-2/Exp8-2.cache/wt/webtalk_pa.xml
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@@ -0,0 +1,57 @@
|
||||
<?xml version="1.0" encoding="UTF-8" ?>
|
||||
<document>
|
||||
<!--The data in this file is primarily intended for consumption by Xilinx tools.
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||||
The structure and the elements are likely to change over the next few releases.
|
||||
This means code written to parse this file will need to be revisited each subsequent release.-->
|
||||
<application name="pa" timeStamp="Wed Dec 18 21:42:34 2024">
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||||
<section name="Project Information" visible="false">
|
||||
<property name="ProjectID" value="cc0fc2ad071840e9be024caf7a6a6a94" type="ProjectID"/>
|
||||
<property name="ProjectIteration" value="1" type="ProjectIteration"/>
|
||||
</section>
|
||||
<section name="PlanAhead Usage" visible="true">
|
||||
<item name="Project Data">
|
||||
<property name="SrcSetCount" value="1" type="SrcSetCount"/>
|
||||
<property name="ConstraintSetCount" value="1" type="ConstraintSetCount"/>
|
||||
<property name="DesignMode" value="RTL" type="DesignMode"/>
|
||||
<property name="SynthesisStrategy" value="Vivado Synthesis Defaults" type="SynthesisStrategy"/>
|
||||
<property name="ImplStrategy" value="Vivado Implementation Defaults" type="ImplStrategy"/>
|
||||
</item>
|
||||
<item name="Java Command Handlers">
|
||||
<property name="AddSources" value="1" type="JavaHandler"/>
|
||||
<property name="NewProject" value="1" type="JavaHandler"/>
|
||||
<property name="OpenProject" value="1" type="JavaHandler"/>
|
||||
<property name="RunSynthesis" value="2" type="JavaHandler"/>
|
||||
<property name="ToolsSettings" value="2" type="JavaHandler"/>
|
||||
<property name="ViewTaskSynthesis" value="2" type="JavaHandler"/>
|
||||
</item>
|
||||
<item name="Gui Handlers">
|
||||
<property name="BaseDialog_CANCEL" value="2" type="GuiHandlerData"/>
|
||||
<property name="BaseDialog_OK" value="7" type="GuiHandlerData"/>
|
||||
<property name="CreateSrcFileDialog_FILE_NAME" value="1" type="GuiHandlerData"/>
|
||||
<property name="FPGAChooser_FPGA_TABLE" value="3" type="GuiHandlerData"/>
|
||||
<property name="FileSetPanel_FILE_SET_PANEL_TREE" value="8" type="GuiHandlerData"/>
|
||||
<property name="FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE" value="3" type="GuiHandlerData"/>
|
||||
<property name="GettingStartedView_CREATE_NEW_PROJECT" value="1" type="GuiHandlerData"/>
|
||||
<property name="MainMenuMgr_CONSTRAINTS" value="1" type="GuiHandlerData"/>
|
||||
<property name="MainMenuMgr_FILE" value="4" type="GuiHandlerData"/>
|
||||
<property name="MainMenuMgr_PROJECT" value="2" type="GuiHandlerData"/>
|
||||
<property name="PACommandNames_AUTO_UPDATE_HIER" value="3" type="GuiHandlerData"/>
|
||||
<property name="PACommandNames_GOTO_NETLIST_DESIGN" value="1" type="GuiHandlerData"/>
|
||||
<property name="PACommandNames_OPEN_PROJECT" value="1" type="GuiHandlerData"/>
|
||||
<property name="ProjectNameChooser_PROJECT_NAME" value="1" type="GuiHandlerData"/>
|
||||
<property name="RDICommands_SETTINGS" value="2" type="GuiHandlerData"/>
|
||||
<property name="SaveProjectUtils_SAVE" value="1" type="GuiHandlerData"/>
|
||||
<property name="SettingsProjectGeneralPage_CHOOSE_DEVICE_FOR_YOUR_PROJECT" value="2" type="GuiHandlerData"/>
|
||||
<property name="SignalTreePanel_SIGNAL_TREE_TABLE" value="27" type="GuiHandlerData"/>
|
||||
<property name="SrcChooserPanel_CREATE_FILE" value="1" type="GuiHandlerData"/>
|
||||
<property name="SrcMenu_IP_HIERARCHY" value="1" type="GuiHandlerData"/>
|
||||
<property name="TaskBanner_CLOSE" value="1" type="GuiHandlerData"/>
|
||||
</item>
|
||||
<item name="Other">
|
||||
<property name="GuiMode" value="3" type="GuiMode"/>
|
||||
<property name="BatchMode" value="0" type="BatchMode"/>
|
||||
<property name="TclMode" value="1" type="TclMode"/>
|
||||
</item>
|
||||
</section>
|
||||
</application>
|
||||
</document>
|
||||
5
Exp8-2/Exp8-2.runs/.jobs/vrs_config_1.xml
Normal file
5
Exp8-2/Exp8-2.runs/.jobs/vrs_config_1.xml
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@@ -0,0 +1,5 @@
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<?xml version="1.0"?>
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<Runs Version="1" Minor="0">
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<Run Id="synth_1" LaunchDir="F:/Schoolwork/DigitalLogic/Exp8-2/Exp8-2.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
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</Runs>
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||||
|
||||
5
Exp8-2/Exp8-2.runs/.jobs/vrs_config_2.xml
Normal file
5
Exp8-2/Exp8-2.runs/.jobs/vrs_config_2.xml
Normal file
@@ -0,0 +1,5 @@
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||||
<?xml version="1.0"?>
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||||
<Runs Version="1" Minor="0">
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<Run Id="synth_1" LaunchDir="F:/Schoolwork/DigitalLogic/Exp8-2/Exp8-2.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
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</Runs>
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||||
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BIN
Exp8-2/Exp8-2.runs/synth_1/date_display.dcp
Normal file
BIN
Exp8-2/Exp8-2.runs/synth_1/date_display.dcp
Normal file
Binary file not shown.
50
Exp8-2/Exp8-2.runs/synth_1/date_display.tcl
Normal file
50
Exp8-2/Exp8-2.runs/synth_1/date_display.tcl
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@@ -0,0 +1,50 @@
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||||
#
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||||
# Synthesis run script generated by Vivado
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||||
#
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||||
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||||
proc create_report { reportName command } {
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||||
set status "."
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||||
append status $reportName ".fail"
|
||||
if { [file exists $status] } {
|
||||
eval file delete [glob $status]
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||||
}
|
||||
send_msg_id runtcl-4 info "Executing : $command"
|
||||
set retval [eval catch { $command } msg]
|
||||
if { $retval != 0 } {
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||||
set fp [open $status w]
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||||
close $fp
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||||
send_msg_id runtcl-5 warning "$msg"
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||||
}
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}
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create_project -in_memory -part xc7a35tcsg324-1
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||||
set_param project.singleFileAddWarning.threshold 0
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set_param project.compositeFile.enableAutoGeneration 0
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||||
set_param synth.vivado.isSynthRun true
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||||
set_property webtalk.parent_dir F:/Schoolwork/DigitalLogic/Exp8-2/Exp8-2.cache/wt [current_project]
|
||||
set_property parent.project_path F:/Schoolwork/DigitalLogic/Exp8-2/Exp8-2.xpr [current_project]
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||||
set_property default_lib xil_defaultlib [current_project]
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||||
set_property target_language Verilog [current_project]
|
||||
set_property ip_output_repo f:/Schoolwork/DigitalLogic/Exp8-2/Exp8-2.cache/ip [current_project]
|
||||
set_property ip_cache_permissions {read write} [current_project]
|
||||
read_verilog -library xil_defaultlib F:/Schoolwork/DigitalLogic/Exp8-2/Exp8-2.srcs/sources_1/new/date_display.v
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# Mark all dcp files as not used in implementation to prevent them from being
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||||
# stitched into the results of this synthesis run. Any black boxes in the
|
||||
# design are intentionally left as such for best results. Dcp files will be
|
||||
# stitched into the design at a later time, either when this synthesis run is
|
||||
# opened, or when it is stitched into a dependent implementation run.
|
||||
foreach dcp [get_files -quiet -all -filter file_type=="Design\ Checkpoint"] {
|
||||
set_property used_in_implementation false $dcp
|
||||
}
|
||||
set_param ips.enableIPCacheLiteLoad 0
|
||||
close [open __synthesis_is_running__ w]
|
||||
|
||||
synth_design -top date_display -part xc7a35tcsg324-1
|
||||
|
||||
|
||||
# disable binary constraint mode for synth run checkpoints
|
||||
set_param constraints.enableBinaryConstraints false
|
||||
write_checkpoint -force -noxdef date_display.dcp
|
||||
create_report "synth_1_synth_report_utilization_0" "report_utilization -file date_display_utilization_synth.rpt -pb date_display_utilization_synth.pb"
|
||||
file delete __synthesis_is_running__
|
||||
close [open __synthesis_is_complete__ w]
|
||||
319
Exp8-2/Exp8-2.runs/synth_1/date_display.vds
Normal file
319
Exp8-2/Exp8-2.runs/synth_1/date_display.vds
Normal file
@@ -0,0 +1,319 @@
|
||||
#-----------------------------------------------------------
|
||||
# Vivado v2018.1 (64-bit)
|
||||
# SW Build 2188600 on Wed Apr 4 18:40:38 MDT 2018
|
||||
# IP Build 2185939 on Wed Apr 4 20:55:05 MDT 2018
|
||||
# Start of session at: Mon Dec 16 19:20:39 2024
|
||||
# Process ID: 20280
|
||||
# Current directory: F:/Schoolwork/DigitalLogic/Exp8-2/Exp8-2.runs/synth_1
|
||||
# Command line: vivado.exe -log date_display.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source date_display.tcl
|
||||
# Log file: F:/Schoolwork/DigitalLogic/Exp8-2/Exp8-2.runs/synth_1/date_display.vds
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||||
# Journal file: F:/Schoolwork/DigitalLogic/Exp8-2/Exp8-2.runs/synth_1\vivado.jou
|
||||
#-----------------------------------------------------------
|
||||
source date_display.tcl -notrace
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||||
Command: synth_design -top date_display -part xc7a35tcsg324-1
|
||||
Starting synth_design
|
||||
Attempting to get a license for feature 'Synthesis' and/or device 'xc7a35t'
|
||||
INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7a35t'
|
||||
INFO: Launching helper process for spawning children vivado processes
|
||||
INFO: Helper process launched with PID 28272
|
||||
---------------------------------------------------------------------------------
|
||||
Starting Synthesize : Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 412.238 ; gain = 98.691
|
||||
---------------------------------------------------------------------------------
|
||||
INFO: [Synth 8-6157] synthesizing module 'date_display' [F:/Schoolwork/DigitalLogic/Exp8-2/Exp8-2.srcs/sources_1/new/date_display.v:23]
|
||||
Parameter S0 bound to: 4'b0000
|
||||
Parameter S1 bound to: 4'b0001
|
||||
Parameter S2 bound to: 4'b0010
|
||||
Parameter S3 bound to: 4'b0011
|
||||
Parameter S4 bound to: 4'b0100
|
||||
Parameter S5 bound to: 4'b0101
|
||||
Parameter S6 bound to: 4'b0110
|
||||
Parameter S7 bound to: 4'b0111
|
||||
Parameter S8 bound to: 4'b1000
|
||||
Parameter S9 bound to: 4'b1001
|
||||
Parameter S10 bound to: 4'b1010
|
||||
Parameter S11 bound to: 4'b1011
|
||||
Parameter S12 bound to: 4'b1100
|
||||
Parameter S13 bound to: 4'b1101
|
||||
Parameter S14 bound to: 4'b1110
|
||||
Parameter S15 bound to: 4'b1111
|
||||
Parameter SEG_0 bound to: 8'b11111101
|
||||
Parameter SEG_1 bound to: 8'b01100001
|
||||
Parameter SEG_2 bound to: 8'b11011011
|
||||
Parameter SEG_3 bound to: 8'b11110011
|
||||
Parameter SEG_4 bound to: 8'b01100111
|
||||
Parameter SEG_5 bound to: 8'b10110111
|
||||
Parameter SEG_6 bound to: 8'b10111111
|
||||
Parameter SEG_7 bound to: 8'b11100001
|
||||
Parameter SEG_8 bound to: 8'b11111111
|
||||
Parameter SEG_9 bound to: 8'b11110111
|
||||
Parameter SEG_DP bound to: 8'b00000001
|
||||
INFO: [Synth 8-226] default block is never used [F:/Schoolwork/DigitalLogic/Exp8-2/Exp8-2.srcs/sources_1/new/date_display.v:93]
|
||||
WARNING: [Synth 8-6014] Unused sequential element seg_temp_reg was removed. [F:/Schoolwork/DigitalLogic/Exp8-2/Exp8-2.srcs/sources_1/new/date_display.v:121]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'date_display' (1#1) [F:/Schoolwork/DigitalLogic/Exp8-2/Exp8-2.srcs/sources_1/new/date_display.v:23]
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Synthesize : Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 466.418 ; gain = 152.871
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Constraint Validation : Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 466.418 ; gain = 152.871
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Loading Part and Timing Information
|
||||
---------------------------------------------------------------------------------
|
||||
Loading part: xc7a35tcsg324-1
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Loading Part and Timing Information : Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 466.418 ; gain = 152.871
|
||||
---------------------------------------------------------------------------------
|
||||
INFO: [Device 21-403] Loading part xc7a35tcsg324-1
|
||||
INFO: [Synth 8-5546] ROM "clk_1hz" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5544] ROM "sequence" won't be mapped to Block RAM because address size (4) smaller than threshold (5)
|
||||
---------------------------------------------------------------------------------
|
||||
Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:04 ; elapsed = 00:00:03 . Memory (MB): peak = 466.418 ; gain = 152.871
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Report RTL Partitions:
|
||||
+-+--------------+------------+----------+
|
||||
| |RTL Partition |Replication |Instances |
|
||||
+-+--------------+------------+----------+
|
||||
+-+--------------+------------+----------+
|
||||
No constraint files found.
|
||||
---------------------------------------------------------------------------------
|
||||
Start RTL Component Statistics
|
||||
---------------------------------------------------------------------------------
|
||||
Detailed RTL Component Info :
|
||||
+---Adders :
|
||||
2 Input 20 Bit Adders := 1
|
||||
+---Registers :
|
||||
20 Bit Registers := 1
|
||||
8 Bit Registers := 2
|
||||
4 Bit Registers := 1
|
||||
1 Bit Registers := 1
|
||||
+---Muxes :
|
||||
17 Input 56 Bit Muxes := 1
|
||||
2 Input 20 Bit Muxes := 1
|
||||
2 Input 1 Bit Muxes := 1
|
||||
---------------------------------------------------------------------------------
|
||||
Finished RTL Component Statistics
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start RTL Hierarchical Component Statistics
|
||||
---------------------------------------------------------------------------------
|
||||
Hierarchical RTL Component report
|
||||
Module date_display
|
||||
Detailed RTL Component Info :
|
||||
+---Adders :
|
||||
2 Input 20 Bit Adders := 1
|
||||
+---Registers :
|
||||
20 Bit Registers := 1
|
||||
8 Bit Registers := 2
|
||||
4 Bit Registers := 1
|
||||
1 Bit Registers := 1
|
||||
+---Muxes :
|
||||
17 Input 56 Bit Muxes := 1
|
||||
2 Input 20 Bit Muxes := 1
|
||||
2 Input 1 Bit Muxes := 1
|
||||
---------------------------------------------------------------------------------
|
||||
Finished RTL Hierarchical Component Statistics
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Part Resource Summary
|
||||
---------------------------------------------------------------------------------
|
||||
Part Resources:
|
||||
DSPs: 90 (col length:60)
|
||||
BRAMs: 100 (col length: RAMB18 60 RAMB36 30)
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Part Resource Summary
|
||||
---------------------------------------------------------------------------------
|
||||
No constraint files found.
|
||||
---------------------------------------------------------------------------------
|
||||
Start Cross Boundary and Area Optimization
|
||||
---------------------------------------------------------------------------------
|
||||
Warning: Parallel synthesis criteria is not met
|
||||
INFO: [Synth 8-5546] ROM "clk_1hz" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-3886] merging instance 'an_reg[0]' (FDP) to 'seg_reg[7]'
|
||||
INFO: [Synth 8-3886] merging instance 'an_reg[1]' (FDP) to 'an_reg[2]'
|
||||
INFO: [Synth 8-3886] merging instance 'an_reg[2]' (FDP) to 'an_reg[3]'
|
||||
INFO: [Synth 8-3886] merging instance 'an_reg[3]' (FDP) to 'an_reg[4]'
|
||||
INFO: [Synth 8-3886] merging instance 'an_reg[4]' (FDP) to 'an_reg[5]'
|
||||
INFO: [Synth 8-3886] merging instance 'an_reg[5]' (FDP) to 'an_reg[6]'
|
||||
INFO: [Synth 8-3886] merging instance 'an_reg[6]' (FDP) to 'an_reg[7]'
|
||||
INFO: [Synth 8-3333] propagating constant 1 across sequential element (\an_reg[7] )
|
||||
INFO: [Synth 8-3886] merging instance 'seg_reg[0]' (FDP) to 'seg_reg[7]'
|
||||
INFO: [Synth 8-3886] merging instance 'seg_reg[1]' (FDP) to 'seg_reg[7]'
|
||||
INFO: [Synth 8-3886] merging instance 'seg_reg[2]' (FDP) to 'seg_reg[7]'
|
||||
INFO: [Synth 8-3886] merging instance 'seg_reg[3]' (FDP) to 'seg_reg[7]'
|
||||
INFO: [Synth 8-3886] merging instance 'seg_reg[4]' (FDP) to 'seg_reg[7]'
|
||||
INFO: [Synth 8-3886] merging instance 'seg_reg[5]' (FDP) to 'seg_reg[7]'
|
||||
INFO: [Synth 8-3886] merging instance 'seg_reg[6]' (FDP) to 'seg_reg[7]'
|
||||
WARNING: [Synth 8-3332] Sequential element (state_c_reg_rep[3]) is unused and will be removed from module date_display.
|
||||
WARNING: [Synth 8-3332] Sequential element (state_c_reg_rep[2]) is unused and will be removed from module date_display.
|
||||
WARNING: [Synth 8-3332] Sequential element (state_c_reg_rep[1]) is unused and will be removed from module date_display.
|
||||
WARNING: [Synth 8-3332] Sequential element (state_c_reg_rep[0]) is unused and will be removed from module date_display.
|
||||
WARNING: [Synth 8-3332] Sequential element (an_reg[7]) is unused and will be removed from module date_display.
|
||||
WARNING: [Synth 8-3332] Sequential element (counter_reg[19]) is unused and will be removed from module date_display.
|
||||
WARNING: [Synth 8-3332] Sequential element (counter_reg[18]) is unused and will be removed from module date_display.
|
||||
WARNING: [Synth 8-3332] Sequential element (counter_reg[17]) is unused and will be removed from module date_display.
|
||||
WARNING: [Synth 8-3332] Sequential element (counter_reg[16]) is unused and will be removed from module date_display.
|
||||
WARNING: [Synth 8-3332] Sequential element (counter_reg[15]) is unused and will be removed from module date_display.
|
||||
WARNING: [Synth 8-3332] Sequential element (counter_reg[14]) is unused and will be removed from module date_display.
|
||||
WARNING: [Synth 8-3332] Sequential element (counter_reg[13]) is unused and will be removed from module date_display.
|
||||
WARNING: [Synth 8-3332] Sequential element (counter_reg[12]) is unused and will be removed from module date_display.
|
||||
WARNING: [Synth 8-3332] Sequential element (counter_reg[11]) is unused and will be removed from module date_display.
|
||||
WARNING: [Synth 8-3332] Sequential element (counter_reg[10]) is unused and will be removed from module date_display.
|
||||
WARNING: [Synth 8-3332] Sequential element (counter_reg[9]) is unused and will be removed from module date_display.
|
||||
WARNING: [Synth 8-3332] Sequential element (counter_reg[8]) is unused and will be removed from module date_display.
|
||||
WARNING: [Synth 8-3332] Sequential element (counter_reg[7]) is unused and will be removed from module date_display.
|
||||
WARNING: [Synth 8-3332] Sequential element (counter_reg[6]) is unused and will be removed from module date_display.
|
||||
WARNING: [Synth 8-3332] Sequential element (counter_reg[5]) is unused and will be removed from module date_display.
|
||||
WARNING: [Synth 8-3332] Sequential element (counter_reg[4]) is unused and will be removed from module date_display.
|
||||
WARNING: [Synth 8-3332] Sequential element (counter_reg[3]) is unused and will be removed from module date_display.
|
||||
WARNING: [Synth 8-3332] Sequential element (counter_reg[2]) is unused and will be removed from module date_display.
|
||||
WARNING: [Synth 8-3332] Sequential element (counter_reg[1]) is unused and will be removed from module date_display.
|
||||
WARNING: [Synth 8-3332] Sequential element (counter_reg[0]) is unused and will be removed from module date_display.
|
||||
WARNING: [Synth 8-3332] Sequential element (clk_1hz_reg) is unused and will be removed from module date_display.
|
||||
WARNING: [Synth 8-3332] Sequential element (state_c_reg[3]) is unused and will be removed from module date_display.
|
||||
WARNING: [Synth 8-3332] Sequential element (state_c_reg[2]) is unused and will be removed from module date_display.
|
||||
WARNING: [Synth 8-3332] Sequential element (state_c_reg[1]) is unused and will be removed from module date_display.
|
||||
WARNING: [Synth 8-3332] Sequential element (state_c_reg[0]) is unused and will be removed from module date_display.
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 586.379 ; gain = 272.832
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Report RTL Partitions:
|
||||
+-+--------------+------------+----------+
|
||||
| |RTL Partition |Replication |Instances |
|
||||
+-+--------------+------------+----------+
|
||||
+-+--------------+------------+----------+
|
||||
No constraint files found.
|
||||
---------------------------------------------------------------------------------
|
||||
Start Timing Optimization
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Timing Optimization : Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 586.379 ; gain = 272.832
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Report RTL Partitions:
|
||||
+-+--------------+------------+----------+
|
||||
| |RTL Partition |Replication |Instances |
|
||||
+-+--------------+------------+----------+
|
||||
+-+--------------+------------+----------+
|
||||
---------------------------------------------------------------------------------
|
||||
Start Technology Mapping
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Technology Mapping : Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 586.379 ; gain = 272.832
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Report RTL Partitions:
|
||||
+-+--------------+------------+----------+
|
||||
| |RTL Partition |Replication |Instances |
|
||||
+-+--------------+------------+----------+
|
||||
+-+--------------+------------+----------+
|
||||
---------------------------------------------------------------------------------
|
||||
Start IO Insertion
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Flattening Before IO Insertion
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Flattening Before IO Insertion
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Final Netlist Cleanup
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Final Netlist Cleanup
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished IO Insertion : Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 586.379 ; gain = 272.832
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Report Check Netlist:
|
||||
+------+------------------+-------+---------+-------+------------------+
|
||||
| |Item |Errors |Warnings |Status |Description |
|
||||
+------+------------------+-------+---------+-------+------------------+
|
||||
|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets |
|
||||
+------+------------------+-------+---------+-------+------------------+
|
||||
---------------------------------------------------------------------------------
|
||||
Start Renaming Generated Instances
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Renaming Generated Instances : Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 586.379 ; gain = 272.832
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Report RTL Partitions:
|
||||
+-+--------------+------------+----------+
|
||||
| |RTL Partition |Replication |Instances |
|
||||
+-+--------------+------------+----------+
|
||||
+-+--------------+------------+----------+
|
||||
---------------------------------------------------------------------------------
|
||||
Start Rebuilding User Hierarchy
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 586.379 ; gain = 272.832
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Renaming Generated Ports
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Renaming Generated Ports : Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 586.379 ; gain = 272.832
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Handling Custom Attributes
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Handling Custom Attributes : Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 586.379 ; gain = 272.832
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Renaming Generated Nets
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Renaming Generated Nets : Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 586.379 ; gain = 272.832
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Writing Synthesis Report
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Report BlackBoxes:
|
||||
+-+--------------+----------+
|
||||
| |BlackBox name |Instances |
|
||||
+-+--------------+----------+
|
||||
+-+--------------+----------+
|
||||
|
||||
Report Cell Usage:
|
||||
+------+-----+------+
|
||||
| |Cell |Count |
|
||||
+------+-----+------+
|
||||
|1 |BUFG | 1|
|
||||
|2 |FDPE | 1|
|
||||
|3 |IBUF | 2|
|
||||
|4 |OBUF | 16|
|
||||
+------+-----+------+
|
||||
|
||||
Report Instance Areas:
|
||||
+------+---------+-------+------+
|
||||
| |Instance |Module |Cells |
|
||||
+------+---------+-------+------+
|
||||
|1 |top | | 20|
|
||||
+------+---------+-------+------+
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Writing Synthesis Report : Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 586.379 ; gain = 272.832
|
||||
---------------------------------------------------------------------------------
|
||||
Synthesis finished with 0 errors, 0 critical warnings and 31 warnings.
|
||||
Synthesis Optimization Runtime : Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 586.379 ; gain = 272.832
|
||||
Synthesis Optimization Complete : Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 586.379 ; gain = 272.832
|
||||
INFO: [Project 1-571] Translating synthesized netlist
|
||||
INFO: [Netlist 29-17] Analyzing 2 Unisim elements for replacement
|
||||
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
|
||||
INFO: [Project 1-570] Preparing netlist for logic optimization
|
||||
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
|
||||
INFO: [Project 1-111] Unisim Transformation Summary:
|
||||
No Unisim elements were transformed.
|
||||
|
||||
INFO: [Common 17-83] Releasing license: Synthesis
|
||||
30 Infos, 31 Warnings, 0 Critical Warnings and 0 Errors encountered.
|
||||
synth_design completed successfully
|
||||
synth_design: Time (s): cpu = 00:00:08 ; elapsed = 00:00:10 . Memory (MB): peak = 692.234 ; gain = 391.566
|
||||
INFO: [Common 17-1381] The checkpoint 'F:/Schoolwork/DigitalLogic/Exp8-2/Exp8-2.runs/synth_1/date_display.dcp' has been generated.
|
||||
INFO: [runtcl-4] Executing : report_utilization -file date_display_utilization_synth.rpt -pb date_display_utilization_synth.pb
|
||||
report_utilization: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.011 . Memory (MB): peak = 692.234 ; gain = 0.000
|
||||
INFO: [Common 17-206] Exiting Vivado at Mon Dec 16 19:20:53 2024...
|
||||
BIN
Exp8-2/Exp8-2.runs/synth_1/date_display_utilization_synth.pb
Normal file
BIN
Exp8-2/Exp8-2.runs/synth_1/date_display_utilization_synth.pb
Normal file
Binary file not shown.
171
Exp8-2/Exp8-2.runs/synth_1/date_display_utilization_synth.rpt
Normal file
171
Exp8-2/Exp8-2.runs/synth_1/date_display_utilization_synth.rpt
Normal file
@@ -0,0 +1,171 @@
|
||||
Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
|
||||
-------------------------------------------------------------------------------------------------------------------
|
||||
| Tool Version : Vivado v.2018.1 (win64) Build 2188600 Wed Apr 4 18:40:38 MDT 2018
|
||||
| Date : Mon Dec 16 19:20:53 2024
|
||||
| Host : W10-20240912132 running 64-bit major release (build 9200)
|
||||
| Command : report_utilization -file date_display_utilization_synth.rpt -pb date_display_utilization_synth.pb
|
||||
| Design : date_display
|
||||
| Device : 7a35tcsg324-1
|
||||
| Design State : Synthesized
|
||||
-------------------------------------------------------------------------------------------------------------------
|
||||
|
||||
Utilization Design Information
|
||||
|
||||
Table of Contents
|
||||
-----------------
|
||||
1. Slice Logic
|
||||
1.1 Summary of Registers by Type
|
||||
2. Memory
|
||||
3. DSP
|
||||
4. IO and GT Specific
|
||||
5. Clocking
|
||||
6. Specific Feature
|
||||
7. Primitives
|
||||
8. Black Boxes
|
||||
9. Instantiated Netlists
|
||||
|
||||
1. Slice Logic
|
||||
--------------
|
||||
|
||||
+-------------------------+------+-------+-----------+-------+
|
||||
| Site Type | Used | Fixed | Available | Util% |
|
||||
+-------------------------+------+-------+-----------+-------+
|
||||
| Slice LUTs* | 0 | 0 | 20800 | 0.00 |
|
||||
| LUT as Logic | 0 | 0 | 20800 | 0.00 |
|
||||
| LUT as Memory | 0 | 0 | 9600 | 0.00 |
|
||||
| Slice Registers | 1 | 0 | 41600 | <0.01 |
|
||||
| Register as Flip Flop | 1 | 0 | 41600 | <0.01 |
|
||||
| Register as Latch | 0 | 0 | 41600 | 0.00 |
|
||||
| F7 Muxes | 0 | 0 | 16300 | 0.00 |
|
||||
| F8 Muxes | 0 | 0 | 8150 | 0.00 |
|
||||
+-------------------------+------+-------+-----------+-------+
|
||||
* Warning! The Final LUT count, after physical optimizations and full implementation, is typically lower. Run opt_design after synthesis, if not already completed, for a more realistic count.
|
||||
|
||||
|
||||
1.1 Summary of Registers by Type
|
||||
--------------------------------
|
||||
|
||||
+-------+--------------+-------------+--------------+
|
||||
| Total | Clock Enable | Synchronous | Asynchronous |
|
||||
+-------+--------------+-------------+--------------+
|
||||
| 0 | _ | - | - |
|
||||
| 0 | _ | - | Set |
|
||||
| 0 | _ | - | Reset |
|
||||
| 0 | _ | Set | - |
|
||||
| 0 | _ | Reset | - |
|
||||
| 0 | Yes | - | - |
|
||||
| 1 | Yes | - | Set |
|
||||
| 0 | Yes | - | Reset |
|
||||
| 0 | Yes | Set | - |
|
||||
| 0 | Yes | Reset | - |
|
||||
+-------+--------------+-------------+--------------+
|
||||
|
||||
|
||||
2. Memory
|
||||
---------
|
||||
|
||||
+----------------+------+-------+-----------+-------+
|
||||
| Site Type | Used | Fixed | Available | Util% |
|
||||
+----------------+------+-------+-----------+-------+
|
||||
| Block RAM Tile | 0 | 0 | 50 | 0.00 |
|
||||
| RAMB36/FIFO* | 0 | 0 | 50 | 0.00 |
|
||||
| RAMB18 | 0 | 0 | 100 | 0.00 |
|
||||
+----------------+------+-------+-----------+-------+
|
||||
* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1
|
||||
|
||||
|
||||
3. DSP
|
||||
------
|
||||
|
||||
+-----------+------+-------+-----------+-------+
|
||||
| Site Type | Used | Fixed | Available | Util% |
|
||||
+-----------+------+-------+-----------+-------+
|
||||
| DSPs | 0 | 0 | 90 | 0.00 |
|
||||
+-----------+------+-------+-----------+-------+
|
||||
|
||||
|
||||
4. IO and GT Specific
|
||||
---------------------
|
||||
|
||||
+-----------------------------+------+-------+-----------+-------+
|
||||
| Site Type | Used | Fixed | Available | Util% |
|
||||
+-----------------------------+------+-------+-----------+-------+
|
||||
| Bonded IOB | 18 | 0 | 210 | 8.57 |
|
||||
| Bonded IPADs | 0 | 0 | 2 | 0.00 |
|
||||
| PHY_CONTROL | 0 | 0 | 5 | 0.00 |
|
||||
| PHASER_REF | 0 | 0 | 5 | 0.00 |
|
||||
| OUT_FIFO | 0 | 0 | 20 | 0.00 |
|
||||
| IN_FIFO | 0 | 0 | 20 | 0.00 |
|
||||
| IDELAYCTRL | 0 | 0 | 5 | 0.00 |
|
||||
| IBUFDS | 0 | 0 | 202 | 0.00 |
|
||||
| PHASER_OUT/PHASER_OUT_PHY | 0 | 0 | 20 | 0.00 |
|
||||
| PHASER_IN/PHASER_IN_PHY | 0 | 0 | 20 | 0.00 |
|
||||
| IDELAYE2/IDELAYE2_FINEDELAY | 0 | 0 | 250 | 0.00 |
|
||||
| ILOGIC | 0 | 0 | 210 | 0.00 |
|
||||
| OLOGIC | 0 | 0 | 210 | 0.00 |
|
||||
+-----------------------------+------+-------+-----------+-------+
|
||||
|
||||
|
||||
5. Clocking
|
||||
-----------
|
||||
|
||||
+------------+------+-------+-----------+-------+
|
||||
| Site Type | Used | Fixed | Available | Util% |
|
||||
+------------+------+-------+-----------+-------+
|
||||
| BUFGCTRL | 1 | 0 | 32 | 3.13 |
|
||||
| BUFIO | 0 | 0 | 20 | 0.00 |
|
||||
| MMCME2_ADV | 0 | 0 | 5 | 0.00 |
|
||||
| PLLE2_ADV | 0 | 0 | 5 | 0.00 |
|
||||
| BUFMRCE | 0 | 0 | 10 | 0.00 |
|
||||
| BUFHCE | 0 | 0 | 72 | 0.00 |
|
||||
| BUFR | 0 | 0 | 20 | 0.00 |
|
||||
+------------+------+-------+-----------+-------+
|
||||
|
||||
|
||||
6. Specific Feature
|
||||
-------------------
|
||||
|
||||
+-------------+------+-------+-----------+-------+
|
||||
| Site Type | Used | Fixed | Available | Util% |
|
||||
+-------------+------+-------+-----------+-------+
|
||||
| BSCANE2 | 0 | 0 | 4 | 0.00 |
|
||||
| CAPTUREE2 | 0 | 0 | 1 | 0.00 |
|
||||
| DNA_PORT | 0 | 0 | 1 | 0.00 |
|
||||
| EFUSE_USR | 0 | 0 | 1 | 0.00 |
|
||||
| FRAME_ECCE2 | 0 | 0 | 1 | 0.00 |
|
||||
| ICAPE2 | 0 | 0 | 2 | 0.00 |
|
||||
| PCIE_2_1 | 0 | 0 | 1 | 0.00 |
|
||||
| STARTUPE2 | 0 | 0 | 1 | 0.00 |
|
||||
| XADC | 0 | 0 | 1 | 0.00 |
|
||||
+-------------+------+-------+-----------+-------+
|
||||
|
||||
|
||||
7. Primitives
|
||||
-------------
|
||||
|
||||
+----------+------+---------------------+
|
||||
| Ref Name | Used | Functional Category |
|
||||
+----------+------+---------------------+
|
||||
| OBUF | 16 | IO |
|
||||
| IBUF | 2 | IO |
|
||||
| FDPE | 1 | Flop & Latch |
|
||||
| BUFG | 1 | Clock |
|
||||
+----------+------+---------------------+
|
||||
|
||||
|
||||
8. Black Boxes
|
||||
--------------
|
||||
|
||||
+----------+------+
|
||||
| Ref Name | Used |
|
||||
+----------+------+
|
||||
|
||||
|
||||
9. Instantiated Netlists
|
||||
------------------------
|
||||
|
||||
+----------+------+
|
||||
| Ref Name | Used |
|
||||
+----------+------+
|
||||
|
||||
|
||||
37
Exp8-2/Exp8-2.runs/synth_1/gen_run.xml
Normal file
37
Exp8-2/Exp8-2.runs/synth_1/gen_run.xml
Normal file
@@ -0,0 +1,37 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<GenRun Id="synth_1" LaunchPart="xc7a35tcsg324-1" LaunchTime="1734348038">
|
||||
<File Type="PA-TCL" Name="date_display.tcl"/>
|
||||
<File Type="RDS-PROPCONSTRS" Name="date_display_drc_synth.rpt"/>
|
||||
<File Type="REPORTS-TCL" Name="date_display_reports.tcl"/>
|
||||
<File Type="RDS-RDS" Name="date_display.vds"/>
|
||||
<File Type="RDS-UTIL" Name="date_display_utilization_synth.rpt"/>
|
||||
<File Type="RDS-UTIL-PB" Name="date_display_utilization_synth.pb"/>
|
||||
<File Type="RDS-DCP" Name="date_display.dcp"/>
|
||||
<File Type="VDS-TIMINGSUMMARY" Name="date_display_timing_summary_synth.rpt"/>
|
||||
<File Type="VDS-TIMING-PB" Name="date_display_timing_summary_synth.pb"/>
|
||||
<FileSet Name="sources" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1">
|
||||
<Filter Type="Srcs"/>
|
||||
<File Path="$PSRCDIR/sources_1/new/date_display.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<Config>
|
||||
<Option Name="DesignMode" Val="RTL"/>
|
||||
<Option Name="TopModule" Val="date_display"/>
|
||||
<Option Name="TopAutoSet" Val="TRUE"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="constrs_in" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1">
|
||||
<Filter Type="Constrs"/>
|
||||
<Config>
|
||||
<Option Name="ConstrsType" Val="XDC"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2018"/>
|
||||
<Step Id="synth_design"/>
|
||||
</Strategy>
|
||||
</GenRun>
|
||||
9
Exp8-2/Exp8-2.runs/synth_1/htr.txt
Normal file
9
Exp8-2/Exp8-2.runs/synth_1/htr.txt
Normal file
@@ -0,0 +1,9 @@
|
||||
REM
|
||||
REM Vivado(TM)
|
||||
REM htr.txt: a Vivado-generated description of how-to-repeat the
|
||||
REM the basic steps of a run. Note that runme.bat/sh needs
|
||||
REM to be invoked for Vivado to track run status.
|
||||
REM Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
|
||||
REM
|
||||
|
||||
vivado -log date_display.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source date_display.tcl
|
||||
12
Exp8-2/Exp8-2.runs/synth_1/vivado.jou
Normal file
12
Exp8-2/Exp8-2.runs/synth_1/vivado.jou
Normal file
@@ -0,0 +1,12 @@
|
||||
#-----------------------------------------------------------
|
||||
# Vivado v2018.1 (64-bit)
|
||||
# SW Build 2188600 on Wed Apr 4 18:40:38 MDT 2018
|
||||
# IP Build 2185939 on Wed Apr 4 20:55:05 MDT 2018
|
||||
# Start of session at: Mon Dec 16 19:20:39 2024
|
||||
# Process ID: 20280
|
||||
# Current directory: F:/Schoolwork/DigitalLogic/Exp8-2/Exp8-2.runs/synth_1
|
||||
# Command line: vivado.exe -log date_display.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source date_display.tcl
|
||||
# Log file: F:/Schoolwork/DigitalLogic/Exp8-2/Exp8-2.runs/synth_1/date_display.vds
|
||||
# Journal file: F:/Schoolwork/DigitalLogic/Exp8-2/Exp8-2.runs/synth_1\vivado.jou
|
||||
#-----------------------------------------------------------
|
||||
source date_display.tcl -notrace
|
||||
BIN
Exp8-2/Exp8-2.runs/synth_1/vivado.pb
Normal file
BIN
Exp8-2/Exp8-2.runs/synth_1/vivado.pb
Normal file
Binary file not shown.
127
Exp8-2/Exp8-2.srcs/sources_1/new/date_display.v
Normal file
127
Exp8-2/Exp8-2.srcs/sources_1/new/date_display.v
Normal file
@@ -0,0 +1,127 @@
|
||||
`timescale 1ns / 1ps
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
// Company:
|
||||
// Engineer:
|
||||
//
|
||||
// Create Date: 2024/12/16 18:24:15
|
||||
// Design Name:
|
||||
// Module Name: date_display
|
||||
// Project Name:
|
||||
// Target Devices:
|
||||
// Tool Versions:
|
||||
// Description:
|
||||
//
|
||||
// Dependencies:
|
||||
//
|
||||
// Revision:
|
||||
// Revision 0.01 - File Created
|
||||
// Additional Comments:
|
||||
//
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
module date_display (
|
||||
input wire clk, // 100 MHz clock input
|
||||
input wire reset, // Reset signal
|
||||
output reg [7:0] seg, // Segment control for 7-segment display
|
||||
output reg [7:0] an // Anode control for dynamic display
|
||||
);
|
||||
|
||||
// State definitions
|
||||
parameter S0 = 4'd0, S1 = 4'd1, S2 = 4'd2, S3 = 4'd3,
|
||||
S4 = 4'd4, S5 = 4'd5, S6 = 4'd6, S7 = 4'd7,
|
||||
S8 = 4'd8, S9 = 4'd9, S10 = 4'd10, S11 = 4'd11,
|
||||
S12 = 4'd12, S13 = 4'd13, S14 = 4'd14, S15 = 4'd15;
|
||||
|
||||
reg [3:0] state_c, state_n; // Current state and next state
|
||||
reg [19:0] counter; // Counter for clock division
|
||||
reg clk_1hz; // 1 Hz clock
|
||||
|
||||
// Segment encoding with dot (decimal point)
|
||||
parameter [7:0] SEG_0 = 8'b11111101, SEG_1 = 8'b01100001, SEG_2 = 8'b11011011,
|
||||
SEG_3 = 8'b11110011, SEG_4 = 8'b01100111, SEG_5 = 8'b10110111,
|
||||
SEG_6 = 8'b10111111, SEG_7 = 8'b11100001, SEG_8 = 8'b11111111,
|
||||
SEG_9 = 8'b11110111, SEG_DP = 8'b00000001;
|
||||
|
||||
// Time sequence for display
|
||||
reg [55:0] sequence [15:0];
|
||||
initial begin
|
||||
sequence[S0] = 56'b00000000_00000000_00000000_00000000_00000000_11111101; // 2
|
||||
sequence[S1] = 56'b00000000_00000000_00000000_00000000_00000011_01100001; // 20
|
||||
sequence[S2] = 56'b00000000_00000000_00000000_00000000_11011011_11110011; // 202
|
||||
sequence[S3] = 56'b00000000_00000000_00000000_00000001_11011011_01100001; // 2024.
|
||||
sequence[S4] = 56'b00000000_00000000_00000000_00001101_10110111_11011011; // 2024.1
|
||||
sequence[S5] = 56'b00000000_00000000_00000110_11011011_10111111_10110111; // 2024.12.
|
||||
sequence[S6] = 56'b00000000_00000000_00001100_11100001_11110011_01100001; // 2024.12.1
|
||||
sequence[S7] = 56'b00000000_00000000_11100001_10111111_11011011_11011011; // 2024.12.16
|
||||
sequence[S8] = 56'b00000000_00000001_11011011_11011011_11011011_10110111; // 024.12.16
|
||||
sequence[S9] = 56'b00000000_00000110_01100001_11100001_11110011_10111111; // 24.12.16
|
||||
sequence[S10] = 56'b00000000_00001111_11110111_11111111_01100001_10111111; // 4.12.16
|
||||
sequence[S11] = 56'b00000000_11111111_11111111_01100111_11111101_01100001; // 12.16
|
||||
sequence[S12] = 56'b11111101_01100001_11111101_01100001_11110111_01100111; // 2.16
|
||||
sequence[S13] = 56'b11110111_11111101_11111111_01100001_01100001_01100001; // 16
|
||||
sequence[S14] = 56'b00000000_11111101_01100001_00000000_00000000_00000000; // 6
|
||||
sequence[S15] = 56'b00000000_00000000_00000000_00000000_00000000_00000000; // Blank
|
||||
end
|
||||
|
||||
// Clock division to generate 1 Hz clock
|
||||
always @(posedge clk or posedge reset) begin
|
||||
if (reset) begin
|
||||
counter <= 0;
|
||||
clk_1hz <= 0;
|
||||
end else begin
|
||||
if (counter == 20'd999_999) begin
|
||||
clk_1hz <= ~clk_1hz;
|
||||
counter <= 0;
|
||||
end else begin
|
||||
counter <= counter + 1;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
// State transition logic
|
||||
always @(posedge clk_1hz or posedge reset) begin
|
||||
if (reset) begin
|
||||
state_c <= S0;
|
||||
end else begin
|
||||
state_c <= state_n;
|
||||
end
|
||||
end
|
||||
|
||||
// Next state logic
|
||||
always @(*) begin
|
||||
case (state_c)
|
||||
S0: state_n = S1;
|
||||
S1: state_n = S2;
|
||||
S2: state_n = S3;
|
||||
S3: state_n = S4;
|
||||
S4: state_n = S5;
|
||||
S5: state_n = S6;
|
||||
S6: state_n = S7;
|
||||
S7: state_n = S8;
|
||||
S8: state_n = S9;
|
||||
S9: state_n = S10;
|
||||
S10: state_n = S11;
|
||||
S11: state_n = S12;
|
||||
S12: state_n = S13;
|
||||
S13: state_n = S14;
|
||||
S14: state_n = S15;
|
||||
S15: state_n = S0;
|
||||
default: state_n = S0;
|
||||
endcase
|
||||
end
|
||||
|
||||
// Output logic for 7-segment display
|
||||
reg [7:0] seg_temp;
|
||||
always @(posedge clk or posedge reset) begin
|
||||
if (reset) begin
|
||||
seg <= 8'b11111111;
|
||||
an <= 8'b11111111;
|
||||
end else begin
|
||||
seg_temp = sequence[state_c][55:48];
|
||||
an <= 8'b11111110; // Activate only one digit (dynamic display)
|
||||
seg <= seg_temp;
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
136
Exp8-2/Exp8-2.xpr
Normal file
136
Exp8-2/Exp8-2.xpr
Normal file
@@ -0,0 +1,136 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<!-- Product Version: Vivado v2018.1 (64-bit) -->
|
||||
<!-- -->
|
||||
<!-- Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. -->
|
||||
|
||||
<Project Version="7" Minor="36" Path="F:/Schoolwork/DigitalLogic/Exp8-2/Exp8-2.xpr">
|
||||
<DefaultLaunch Dir="$PRUNDIR"/>
|
||||
<Configuration>
|
||||
<Option Name="Id" Val="5c094be9582246afa360090f23c211ed"/>
|
||||
<Option Name="Part" Val="xc7a35tcsg324-1"/>
|
||||
<Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
|
||||
<Option Name="CompiledLibDirXSim" Val=""/>
|
||||
<Option Name="CompiledLibDirModelSim" Val="$PCACHEDIR/compile_simlib/modelsim"/>
|
||||
<Option Name="CompiledLibDirQuesta" Val="$PCACHEDIR/compile_simlib/questa"/>
|
||||
<Option Name="CompiledLibDirIES" Val="$PCACHEDIR/compile_simlib/ies"/>
|
||||
<Option Name="CompiledLibDirXcelium" Val="$PCACHEDIR/compile_simlib/xcelium"/>
|
||||
<Option Name="CompiledLibDirVCS" Val="$PCACHEDIR/compile_simlib/vcs"/>
|
||||
<Option Name="CompiledLibDirRiviera" Val="$PCACHEDIR/compile_simlib/riviera"/>
|
||||
<Option Name="CompiledLibDirActivehdl" Val="$PCACHEDIR/compile_simlib/activehdl"/>
|
||||
<Option Name="BoardPart" Val=""/>
|
||||
<Option Name="ActiveSimSet" Val="sim_1"/>
|
||||
<Option Name="DefaultLib" Val="xil_defaultlib"/>
|
||||
<Option Name="ProjectType" Val="Default"/>
|
||||
<Option Name="IPOutputRepo" Val="$PCACHEDIR/ip"/>
|
||||
<Option Name="IPCachePermission" Val="read"/>
|
||||
<Option Name="IPCachePermission" Val="write"/>
|
||||
<Option Name="EnableCoreContainer" Val="FALSE"/>
|
||||
<Option Name="CreateRefXciForCoreContainers" Val="FALSE"/>
|
||||
<Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
|
||||
<Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
|
||||
<Option Name="EnableBDX" Val="FALSE"/>
|
||||
<Option Name="DSAVendor" Val="xilinx"/>
|
||||
<Option Name="DSANumComputeUnits" Val="60"/>
|
||||
<Option Name="WTXSimLaunchSim" Val="0"/>
|
||||
<Option Name="WTModelSimLaunchSim" Val="0"/>
|
||||
<Option Name="WTQuestaLaunchSim" Val="0"/>
|
||||
<Option Name="WTIesLaunchSim" Val="0"/>
|
||||
<Option Name="WTVcsLaunchSim" Val="0"/>
|
||||
<Option Name="WTRivieraLaunchSim" Val="0"/>
|
||||
<Option Name="WTActivehdlLaunchSim" Val="0"/>
|
||||
<Option Name="WTXSimExportSim" Val="0"/>
|
||||
<Option Name="WTModelSimExportSim" Val="0"/>
|
||||
<Option Name="WTQuestaExportSim" Val="0"/>
|
||||
<Option Name="WTIesExportSim" Val="0"/>
|
||||
<Option Name="WTVcsExportSim" Val="0"/>
|
||||
<Option Name="WTRivieraExportSim" Val="0"/>
|
||||
<Option Name="WTActivehdlExportSim" Val="0"/>
|
||||
<Option Name="GenerateIPUpgradeLog" Val="TRUE"/>
|
||||
<Option Name="XSimRadix" Val="hex"/>
|
||||
<Option Name="XSimTimeUnit" Val="ns"/>
|
||||
<Option Name="XSimArrayDisplayLimit" Val="1024"/>
|
||||
<Option Name="XSimTraceLimit" Val="65536"/>
|
||||
<Option Name="SimTypes" Val="rtl"/>
|
||||
</Configuration>
|
||||
<FileSets Version="1" Minor="31">
|
||||
<FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1">
|
||||
<Filter Type="Srcs"/>
|
||||
<File Path="$PSRCDIR/sources_1/new/date_display.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<Config>
|
||||
<Option Name="DesignMode" Val="RTL"/>
|
||||
<Option Name="TopModule" Val="date_display"/>
|
||||
<Option Name="TopAutoSet" Val="TRUE"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1">
|
||||
<Filter Type="Constrs"/>
|
||||
<Config>
|
||||
<Option Name="ConstrsType" Val="XDC"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1">
|
||||
<Filter Type="Srcs"/>
|
||||
<Config>
|
||||
<Option Name="DesignMode" Val="RTL"/>
|
||||
<Option Name="TopModule" Val="date_display"/>
|
||||
<Option Name="TopLib" Val="xil_defaultlib"/>
|
||||
<Option Name="TopAutoSet" Val="TRUE"/>
|
||||
<Option Name="TransportPathDelay" Val="0"/>
|
||||
<Option Name="TransportIntDelay" Val="0"/>
|
||||
<Option Name="SrcSet" Val="sources_1"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
</FileSets>
|
||||
<Simulators>
|
||||
<Simulator Name="XSim">
|
||||
<Option Name="Description" Val="Vivado Simulator"/>
|
||||
<Option Name="CompiledLib" Val="0"/>
|
||||
</Simulator>
|
||||
<Simulator Name="ModelSim">
|
||||
<Option Name="Description" Val="ModelSim Simulator"/>
|
||||
</Simulator>
|
||||
<Simulator Name="Questa">
|
||||
<Option Name="Description" Val="Questa Advanced Simulator"/>
|
||||
</Simulator>
|
||||
<Simulator Name="Riviera">
|
||||
<Option Name="Description" Val="Riviera-PRO Simulator"/>
|
||||
</Simulator>
|
||||
<Simulator Name="ActiveHDL">
|
||||
<Option Name="Description" Val="Active-HDL Simulator"/>
|
||||
</Simulator>
|
||||
</Simulators>
|
||||
<Runs Version="1" Minor="10">
|
||||
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7a35tcsg324-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/synth_1" IncludeInArchive="true">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2018"/>
|
||||
<Step Id="synth_design"/>
|
||||
</Strategy>
|
||||
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
|
||||
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2018"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
</Run>
|
||||
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7a35tcsg324-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2018"/>
|
||||
<Step Id="init_design"/>
|
||||
<Step Id="opt_design"/>
|
||||
<Step Id="power_opt_design"/>
|
||||
<Step Id="place_design"/>
|
||||
<Step Id="post_place_power_opt_design"/>
|
||||
<Step Id="phys_opt_design"/>
|
||||
<Step Id="route_design"/>
|
||||
<Step Id="post_route_phys_opt_design"/>
|
||||
<Step Id="write_bitstream"/>
|
||||
</Strategy>
|
||||
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2018"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
</Run>
|
||||
</Runs>
|
||||
<Board/>
|
||||
</Project>
|
||||
14
Exp8-2/vivado.jou
Normal file
14
Exp8-2/vivado.jou
Normal file
@@ -0,0 +1,14 @@
|
||||
#-----------------------------------------------------------
|
||||
# Vivado v2018.1 (64-bit)
|
||||
# SW Build 2188600 on Wed Apr 4 18:40:38 MDT 2018
|
||||
# IP Build 2185939 on Wed Apr 4 20:55:05 MDT 2018
|
||||
# Start of session at: Wed Dec 18 21:40:31 2024
|
||||
# Process ID: 888
|
||||
# Current directory: E:/Schoolwork/DigitalLogic/Exp8-2
|
||||
# Command line: vivado.exe -gui_launcher_event rodinguilauncherevent14032 E:\Schoolwork\DigitalLogic\Exp8-2\Exp8-2.xpr
|
||||
# Log file: E:/Schoolwork/DigitalLogic/Exp8-2/vivado.log
|
||||
# Journal file: E:/Schoolwork/DigitalLogic/Exp8-2\vivado.jou
|
||||
#-----------------------------------------------------------
|
||||
start_gui
|
||||
open_project E:/Schoolwork/DigitalLogic/Exp8-2/Exp8-2.xpr
|
||||
update_compile_order -fileset sources_1
|
||||
Reference in New Issue
Block a user