Initial commit
This commit is contained in:
BIN
Exp8-2/Exp8-2.runs/synth_1/date_display.dcp
Normal file
BIN
Exp8-2/Exp8-2.runs/synth_1/date_display.dcp
Normal file
Binary file not shown.
50
Exp8-2/Exp8-2.runs/synth_1/date_display.tcl
Normal file
50
Exp8-2/Exp8-2.runs/synth_1/date_display.tcl
Normal file
@@ -0,0 +1,50 @@
|
||||
#
|
||||
# Synthesis run script generated by Vivado
|
||||
#
|
||||
|
||||
proc create_report { reportName command } {
|
||||
set status "."
|
||||
append status $reportName ".fail"
|
||||
if { [file exists $status] } {
|
||||
eval file delete [glob $status]
|
||||
}
|
||||
send_msg_id runtcl-4 info "Executing : $command"
|
||||
set retval [eval catch { $command } msg]
|
||||
if { $retval != 0 } {
|
||||
set fp [open $status w]
|
||||
close $fp
|
||||
send_msg_id runtcl-5 warning "$msg"
|
||||
}
|
||||
}
|
||||
create_project -in_memory -part xc7a35tcsg324-1
|
||||
|
||||
set_param project.singleFileAddWarning.threshold 0
|
||||
set_param project.compositeFile.enableAutoGeneration 0
|
||||
set_param synth.vivado.isSynthRun true
|
||||
set_property webtalk.parent_dir F:/Schoolwork/DigitalLogic/Exp8-2/Exp8-2.cache/wt [current_project]
|
||||
set_property parent.project_path F:/Schoolwork/DigitalLogic/Exp8-2/Exp8-2.xpr [current_project]
|
||||
set_property default_lib xil_defaultlib [current_project]
|
||||
set_property target_language Verilog [current_project]
|
||||
set_property ip_output_repo f:/Schoolwork/DigitalLogic/Exp8-2/Exp8-2.cache/ip [current_project]
|
||||
set_property ip_cache_permissions {read write} [current_project]
|
||||
read_verilog -library xil_defaultlib F:/Schoolwork/DigitalLogic/Exp8-2/Exp8-2.srcs/sources_1/new/date_display.v
|
||||
# Mark all dcp files as not used in implementation to prevent them from being
|
||||
# stitched into the results of this synthesis run. Any black boxes in the
|
||||
# design are intentionally left as such for best results. Dcp files will be
|
||||
# stitched into the design at a later time, either when this synthesis run is
|
||||
# opened, or when it is stitched into a dependent implementation run.
|
||||
foreach dcp [get_files -quiet -all -filter file_type=="Design\ Checkpoint"] {
|
||||
set_property used_in_implementation false $dcp
|
||||
}
|
||||
set_param ips.enableIPCacheLiteLoad 0
|
||||
close [open __synthesis_is_running__ w]
|
||||
|
||||
synth_design -top date_display -part xc7a35tcsg324-1
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||||
|
||||
|
||||
# disable binary constraint mode for synth run checkpoints
|
||||
set_param constraints.enableBinaryConstraints false
|
||||
write_checkpoint -force -noxdef date_display.dcp
|
||||
create_report "synth_1_synth_report_utilization_0" "report_utilization -file date_display_utilization_synth.rpt -pb date_display_utilization_synth.pb"
|
||||
file delete __synthesis_is_running__
|
||||
close [open __synthesis_is_complete__ w]
|
||||
319
Exp8-2/Exp8-2.runs/synth_1/date_display.vds
Normal file
319
Exp8-2/Exp8-2.runs/synth_1/date_display.vds
Normal file
@@ -0,0 +1,319 @@
|
||||
#-----------------------------------------------------------
|
||||
# Vivado v2018.1 (64-bit)
|
||||
# SW Build 2188600 on Wed Apr 4 18:40:38 MDT 2018
|
||||
# IP Build 2185939 on Wed Apr 4 20:55:05 MDT 2018
|
||||
# Start of session at: Mon Dec 16 19:20:39 2024
|
||||
# Process ID: 20280
|
||||
# Current directory: F:/Schoolwork/DigitalLogic/Exp8-2/Exp8-2.runs/synth_1
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||||
# Command line: vivado.exe -log date_display.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source date_display.tcl
|
||||
# Log file: F:/Schoolwork/DigitalLogic/Exp8-2/Exp8-2.runs/synth_1/date_display.vds
|
||||
# Journal file: F:/Schoolwork/DigitalLogic/Exp8-2/Exp8-2.runs/synth_1\vivado.jou
|
||||
#-----------------------------------------------------------
|
||||
source date_display.tcl -notrace
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||||
Command: synth_design -top date_display -part xc7a35tcsg324-1
|
||||
Starting synth_design
|
||||
Attempting to get a license for feature 'Synthesis' and/or device 'xc7a35t'
|
||||
INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7a35t'
|
||||
INFO: Launching helper process for spawning children vivado processes
|
||||
INFO: Helper process launched with PID 28272
|
||||
---------------------------------------------------------------------------------
|
||||
Starting Synthesize : Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 412.238 ; gain = 98.691
|
||||
---------------------------------------------------------------------------------
|
||||
INFO: [Synth 8-6157] synthesizing module 'date_display' [F:/Schoolwork/DigitalLogic/Exp8-2/Exp8-2.srcs/sources_1/new/date_display.v:23]
|
||||
Parameter S0 bound to: 4'b0000
|
||||
Parameter S1 bound to: 4'b0001
|
||||
Parameter S2 bound to: 4'b0010
|
||||
Parameter S3 bound to: 4'b0011
|
||||
Parameter S4 bound to: 4'b0100
|
||||
Parameter S5 bound to: 4'b0101
|
||||
Parameter S6 bound to: 4'b0110
|
||||
Parameter S7 bound to: 4'b0111
|
||||
Parameter S8 bound to: 4'b1000
|
||||
Parameter S9 bound to: 4'b1001
|
||||
Parameter S10 bound to: 4'b1010
|
||||
Parameter S11 bound to: 4'b1011
|
||||
Parameter S12 bound to: 4'b1100
|
||||
Parameter S13 bound to: 4'b1101
|
||||
Parameter S14 bound to: 4'b1110
|
||||
Parameter S15 bound to: 4'b1111
|
||||
Parameter SEG_0 bound to: 8'b11111101
|
||||
Parameter SEG_1 bound to: 8'b01100001
|
||||
Parameter SEG_2 bound to: 8'b11011011
|
||||
Parameter SEG_3 bound to: 8'b11110011
|
||||
Parameter SEG_4 bound to: 8'b01100111
|
||||
Parameter SEG_5 bound to: 8'b10110111
|
||||
Parameter SEG_6 bound to: 8'b10111111
|
||||
Parameter SEG_7 bound to: 8'b11100001
|
||||
Parameter SEG_8 bound to: 8'b11111111
|
||||
Parameter SEG_9 bound to: 8'b11110111
|
||||
Parameter SEG_DP bound to: 8'b00000001
|
||||
INFO: [Synth 8-226] default block is never used [F:/Schoolwork/DigitalLogic/Exp8-2/Exp8-2.srcs/sources_1/new/date_display.v:93]
|
||||
WARNING: [Synth 8-6014] Unused sequential element seg_temp_reg was removed. [F:/Schoolwork/DigitalLogic/Exp8-2/Exp8-2.srcs/sources_1/new/date_display.v:121]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'date_display' (1#1) [F:/Schoolwork/DigitalLogic/Exp8-2/Exp8-2.srcs/sources_1/new/date_display.v:23]
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Synthesize : Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 466.418 ; gain = 152.871
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Constraint Validation : Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 466.418 ; gain = 152.871
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Loading Part and Timing Information
|
||||
---------------------------------------------------------------------------------
|
||||
Loading part: xc7a35tcsg324-1
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Loading Part and Timing Information : Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 466.418 ; gain = 152.871
|
||||
---------------------------------------------------------------------------------
|
||||
INFO: [Device 21-403] Loading part xc7a35tcsg324-1
|
||||
INFO: [Synth 8-5546] ROM "clk_1hz" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5544] ROM "sequence" won't be mapped to Block RAM because address size (4) smaller than threshold (5)
|
||||
---------------------------------------------------------------------------------
|
||||
Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:04 ; elapsed = 00:00:03 . Memory (MB): peak = 466.418 ; gain = 152.871
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Report RTL Partitions:
|
||||
+-+--------------+------------+----------+
|
||||
| |RTL Partition |Replication |Instances |
|
||||
+-+--------------+------------+----------+
|
||||
+-+--------------+------------+----------+
|
||||
No constraint files found.
|
||||
---------------------------------------------------------------------------------
|
||||
Start RTL Component Statistics
|
||||
---------------------------------------------------------------------------------
|
||||
Detailed RTL Component Info :
|
||||
+---Adders :
|
||||
2 Input 20 Bit Adders := 1
|
||||
+---Registers :
|
||||
20 Bit Registers := 1
|
||||
8 Bit Registers := 2
|
||||
4 Bit Registers := 1
|
||||
1 Bit Registers := 1
|
||||
+---Muxes :
|
||||
17 Input 56 Bit Muxes := 1
|
||||
2 Input 20 Bit Muxes := 1
|
||||
2 Input 1 Bit Muxes := 1
|
||||
---------------------------------------------------------------------------------
|
||||
Finished RTL Component Statistics
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start RTL Hierarchical Component Statistics
|
||||
---------------------------------------------------------------------------------
|
||||
Hierarchical RTL Component report
|
||||
Module date_display
|
||||
Detailed RTL Component Info :
|
||||
+---Adders :
|
||||
2 Input 20 Bit Adders := 1
|
||||
+---Registers :
|
||||
20 Bit Registers := 1
|
||||
8 Bit Registers := 2
|
||||
4 Bit Registers := 1
|
||||
1 Bit Registers := 1
|
||||
+---Muxes :
|
||||
17 Input 56 Bit Muxes := 1
|
||||
2 Input 20 Bit Muxes := 1
|
||||
2 Input 1 Bit Muxes := 1
|
||||
---------------------------------------------------------------------------------
|
||||
Finished RTL Hierarchical Component Statistics
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Part Resource Summary
|
||||
---------------------------------------------------------------------------------
|
||||
Part Resources:
|
||||
DSPs: 90 (col length:60)
|
||||
BRAMs: 100 (col length: RAMB18 60 RAMB36 30)
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Part Resource Summary
|
||||
---------------------------------------------------------------------------------
|
||||
No constraint files found.
|
||||
---------------------------------------------------------------------------------
|
||||
Start Cross Boundary and Area Optimization
|
||||
---------------------------------------------------------------------------------
|
||||
Warning: Parallel synthesis criteria is not met
|
||||
INFO: [Synth 8-5546] ROM "clk_1hz" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-3886] merging instance 'an_reg[0]' (FDP) to 'seg_reg[7]'
|
||||
INFO: [Synth 8-3886] merging instance 'an_reg[1]' (FDP) to 'an_reg[2]'
|
||||
INFO: [Synth 8-3886] merging instance 'an_reg[2]' (FDP) to 'an_reg[3]'
|
||||
INFO: [Synth 8-3886] merging instance 'an_reg[3]' (FDP) to 'an_reg[4]'
|
||||
INFO: [Synth 8-3886] merging instance 'an_reg[4]' (FDP) to 'an_reg[5]'
|
||||
INFO: [Synth 8-3886] merging instance 'an_reg[5]' (FDP) to 'an_reg[6]'
|
||||
INFO: [Synth 8-3886] merging instance 'an_reg[6]' (FDP) to 'an_reg[7]'
|
||||
INFO: [Synth 8-3333] propagating constant 1 across sequential element (\an_reg[7] )
|
||||
INFO: [Synth 8-3886] merging instance 'seg_reg[0]' (FDP) to 'seg_reg[7]'
|
||||
INFO: [Synth 8-3886] merging instance 'seg_reg[1]' (FDP) to 'seg_reg[7]'
|
||||
INFO: [Synth 8-3886] merging instance 'seg_reg[2]' (FDP) to 'seg_reg[7]'
|
||||
INFO: [Synth 8-3886] merging instance 'seg_reg[3]' (FDP) to 'seg_reg[7]'
|
||||
INFO: [Synth 8-3886] merging instance 'seg_reg[4]' (FDP) to 'seg_reg[7]'
|
||||
INFO: [Synth 8-3886] merging instance 'seg_reg[5]' (FDP) to 'seg_reg[7]'
|
||||
INFO: [Synth 8-3886] merging instance 'seg_reg[6]' (FDP) to 'seg_reg[7]'
|
||||
WARNING: [Synth 8-3332] Sequential element (state_c_reg_rep[3]) is unused and will be removed from module date_display.
|
||||
WARNING: [Synth 8-3332] Sequential element (state_c_reg_rep[2]) is unused and will be removed from module date_display.
|
||||
WARNING: [Synth 8-3332] Sequential element (state_c_reg_rep[1]) is unused and will be removed from module date_display.
|
||||
WARNING: [Synth 8-3332] Sequential element (state_c_reg_rep[0]) is unused and will be removed from module date_display.
|
||||
WARNING: [Synth 8-3332] Sequential element (an_reg[7]) is unused and will be removed from module date_display.
|
||||
WARNING: [Synth 8-3332] Sequential element (counter_reg[19]) is unused and will be removed from module date_display.
|
||||
WARNING: [Synth 8-3332] Sequential element (counter_reg[18]) is unused and will be removed from module date_display.
|
||||
WARNING: [Synth 8-3332] Sequential element (counter_reg[17]) is unused and will be removed from module date_display.
|
||||
WARNING: [Synth 8-3332] Sequential element (counter_reg[16]) is unused and will be removed from module date_display.
|
||||
WARNING: [Synth 8-3332] Sequential element (counter_reg[15]) is unused and will be removed from module date_display.
|
||||
WARNING: [Synth 8-3332] Sequential element (counter_reg[14]) is unused and will be removed from module date_display.
|
||||
WARNING: [Synth 8-3332] Sequential element (counter_reg[13]) is unused and will be removed from module date_display.
|
||||
WARNING: [Synth 8-3332] Sequential element (counter_reg[12]) is unused and will be removed from module date_display.
|
||||
WARNING: [Synth 8-3332] Sequential element (counter_reg[11]) is unused and will be removed from module date_display.
|
||||
WARNING: [Synth 8-3332] Sequential element (counter_reg[10]) is unused and will be removed from module date_display.
|
||||
WARNING: [Synth 8-3332] Sequential element (counter_reg[9]) is unused and will be removed from module date_display.
|
||||
WARNING: [Synth 8-3332] Sequential element (counter_reg[8]) is unused and will be removed from module date_display.
|
||||
WARNING: [Synth 8-3332] Sequential element (counter_reg[7]) is unused and will be removed from module date_display.
|
||||
WARNING: [Synth 8-3332] Sequential element (counter_reg[6]) is unused and will be removed from module date_display.
|
||||
WARNING: [Synth 8-3332] Sequential element (counter_reg[5]) is unused and will be removed from module date_display.
|
||||
WARNING: [Synth 8-3332] Sequential element (counter_reg[4]) is unused and will be removed from module date_display.
|
||||
WARNING: [Synth 8-3332] Sequential element (counter_reg[3]) is unused and will be removed from module date_display.
|
||||
WARNING: [Synth 8-3332] Sequential element (counter_reg[2]) is unused and will be removed from module date_display.
|
||||
WARNING: [Synth 8-3332] Sequential element (counter_reg[1]) is unused and will be removed from module date_display.
|
||||
WARNING: [Synth 8-3332] Sequential element (counter_reg[0]) is unused and will be removed from module date_display.
|
||||
WARNING: [Synth 8-3332] Sequential element (clk_1hz_reg) is unused and will be removed from module date_display.
|
||||
WARNING: [Synth 8-3332] Sequential element (state_c_reg[3]) is unused and will be removed from module date_display.
|
||||
WARNING: [Synth 8-3332] Sequential element (state_c_reg[2]) is unused and will be removed from module date_display.
|
||||
WARNING: [Synth 8-3332] Sequential element (state_c_reg[1]) is unused and will be removed from module date_display.
|
||||
WARNING: [Synth 8-3332] Sequential element (state_c_reg[0]) is unused and will be removed from module date_display.
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 586.379 ; gain = 272.832
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Report RTL Partitions:
|
||||
+-+--------------+------------+----------+
|
||||
| |RTL Partition |Replication |Instances |
|
||||
+-+--------------+------------+----------+
|
||||
+-+--------------+------------+----------+
|
||||
No constraint files found.
|
||||
---------------------------------------------------------------------------------
|
||||
Start Timing Optimization
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Timing Optimization : Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 586.379 ; gain = 272.832
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Report RTL Partitions:
|
||||
+-+--------------+------------+----------+
|
||||
| |RTL Partition |Replication |Instances |
|
||||
+-+--------------+------------+----------+
|
||||
+-+--------------+------------+----------+
|
||||
---------------------------------------------------------------------------------
|
||||
Start Technology Mapping
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Technology Mapping : Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 586.379 ; gain = 272.832
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Report RTL Partitions:
|
||||
+-+--------------+------------+----------+
|
||||
| |RTL Partition |Replication |Instances |
|
||||
+-+--------------+------------+----------+
|
||||
+-+--------------+------------+----------+
|
||||
---------------------------------------------------------------------------------
|
||||
Start IO Insertion
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Flattening Before IO Insertion
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Flattening Before IO Insertion
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Final Netlist Cleanup
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Final Netlist Cleanup
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished IO Insertion : Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 586.379 ; gain = 272.832
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Report Check Netlist:
|
||||
+------+------------------+-------+---------+-------+------------------+
|
||||
| |Item |Errors |Warnings |Status |Description |
|
||||
+------+------------------+-------+---------+-------+------------------+
|
||||
|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets |
|
||||
+------+------------------+-------+---------+-------+------------------+
|
||||
---------------------------------------------------------------------------------
|
||||
Start Renaming Generated Instances
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Renaming Generated Instances : Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 586.379 ; gain = 272.832
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Report RTL Partitions:
|
||||
+-+--------------+------------+----------+
|
||||
| |RTL Partition |Replication |Instances |
|
||||
+-+--------------+------------+----------+
|
||||
+-+--------------+------------+----------+
|
||||
---------------------------------------------------------------------------------
|
||||
Start Rebuilding User Hierarchy
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 586.379 ; gain = 272.832
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Renaming Generated Ports
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Renaming Generated Ports : Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 586.379 ; gain = 272.832
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Handling Custom Attributes
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Handling Custom Attributes : Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 586.379 ; gain = 272.832
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Renaming Generated Nets
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Renaming Generated Nets : Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 586.379 ; gain = 272.832
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Writing Synthesis Report
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Report BlackBoxes:
|
||||
+-+--------------+----------+
|
||||
| |BlackBox name |Instances |
|
||||
+-+--------------+----------+
|
||||
+-+--------------+----------+
|
||||
|
||||
Report Cell Usage:
|
||||
+------+-----+------+
|
||||
| |Cell |Count |
|
||||
+------+-----+------+
|
||||
|1 |BUFG | 1|
|
||||
|2 |FDPE | 1|
|
||||
|3 |IBUF | 2|
|
||||
|4 |OBUF | 16|
|
||||
+------+-----+------+
|
||||
|
||||
Report Instance Areas:
|
||||
+------+---------+-------+------+
|
||||
| |Instance |Module |Cells |
|
||||
+------+---------+-------+------+
|
||||
|1 |top | | 20|
|
||||
+------+---------+-------+------+
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Writing Synthesis Report : Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 586.379 ; gain = 272.832
|
||||
---------------------------------------------------------------------------------
|
||||
Synthesis finished with 0 errors, 0 critical warnings and 31 warnings.
|
||||
Synthesis Optimization Runtime : Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 586.379 ; gain = 272.832
|
||||
Synthesis Optimization Complete : Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 586.379 ; gain = 272.832
|
||||
INFO: [Project 1-571] Translating synthesized netlist
|
||||
INFO: [Netlist 29-17] Analyzing 2 Unisim elements for replacement
|
||||
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
|
||||
INFO: [Project 1-570] Preparing netlist for logic optimization
|
||||
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
|
||||
INFO: [Project 1-111] Unisim Transformation Summary:
|
||||
No Unisim elements were transformed.
|
||||
|
||||
INFO: [Common 17-83] Releasing license: Synthesis
|
||||
30 Infos, 31 Warnings, 0 Critical Warnings and 0 Errors encountered.
|
||||
synth_design completed successfully
|
||||
synth_design: Time (s): cpu = 00:00:08 ; elapsed = 00:00:10 . Memory (MB): peak = 692.234 ; gain = 391.566
|
||||
INFO: [Common 17-1381] The checkpoint 'F:/Schoolwork/DigitalLogic/Exp8-2/Exp8-2.runs/synth_1/date_display.dcp' has been generated.
|
||||
INFO: [runtcl-4] Executing : report_utilization -file date_display_utilization_synth.rpt -pb date_display_utilization_synth.pb
|
||||
report_utilization: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.011 . Memory (MB): peak = 692.234 ; gain = 0.000
|
||||
INFO: [Common 17-206] Exiting Vivado at Mon Dec 16 19:20:53 2024...
|
||||
BIN
Exp8-2/Exp8-2.runs/synth_1/date_display_utilization_synth.pb
Normal file
BIN
Exp8-2/Exp8-2.runs/synth_1/date_display_utilization_synth.pb
Normal file
Binary file not shown.
171
Exp8-2/Exp8-2.runs/synth_1/date_display_utilization_synth.rpt
Normal file
171
Exp8-2/Exp8-2.runs/synth_1/date_display_utilization_synth.rpt
Normal file
@@ -0,0 +1,171 @@
|
||||
Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
|
||||
-------------------------------------------------------------------------------------------------------------------
|
||||
| Tool Version : Vivado v.2018.1 (win64) Build 2188600 Wed Apr 4 18:40:38 MDT 2018
|
||||
| Date : Mon Dec 16 19:20:53 2024
|
||||
| Host : W10-20240912132 running 64-bit major release (build 9200)
|
||||
| Command : report_utilization -file date_display_utilization_synth.rpt -pb date_display_utilization_synth.pb
|
||||
| Design : date_display
|
||||
| Device : 7a35tcsg324-1
|
||||
| Design State : Synthesized
|
||||
-------------------------------------------------------------------------------------------------------------------
|
||||
|
||||
Utilization Design Information
|
||||
|
||||
Table of Contents
|
||||
-----------------
|
||||
1. Slice Logic
|
||||
1.1 Summary of Registers by Type
|
||||
2. Memory
|
||||
3. DSP
|
||||
4. IO and GT Specific
|
||||
5. Clocking
|
||||
6. Specific Feature
|
||||
7. Primitives
|
||||
8. Black Boxes
|
||||
9. Instantiated Netlists
|
||||
|
||||
1. Slice Logic
|
||||
--------------
|
||||
|
||||
+-------------------------+------+-------+-----------+-------+
|
||||
| Site Type | Used | Fixed | Available | Util% |
|
||||
+-------------------------+------+-------+-----------+-------+
|
||||
| Slice LUTs* | 0 | 0 | 20800 | 0.00 |
|
||||
| LUT as Logic | 0 | 0 | 20800 | 0.00 |
|
||||
| LUT as Memory | 0 | 0 | 9600 | 0.00 |
|
||||
| Slice Registers | 1 | 0 | 41600 | <0.01 |
|
||||
| Register as Flip Flop | 1 | 0 | 41600 | <0.01 |
|
||||
| Register as Latch | 0 | 0 | 41600 | 0.00 |
|
||||
| F7 Muxes | 0 | 0 | 16300 | 0.00 |
|
||||
| F8 Muxes | 0 | 0 | 8150 | 0.00 |
|
||||
+-------------------------+------+-------+-----------+-------+
|
||||
* Warning! The Final LUT count, after physical optimizations and full implementation, is typically lower. Run opt_design after synthesis, if not already completed, for a more realistic count.
|
||||
|
||||
|
||||
1.1 Summary of Registers by Type
|
||||
--------------------------------
|
||||
|
||||
+-------+--------------+-------------+--------------+
|
||||
| Total | Clock Enable | Synchronous | Asynchronous |
|
||||
+-------+--------------+-------------+--------------+
|
||||
| 0 | _ | - | - |
|
||||
| 0 | _ | - | Set |
|
||||
| 0 | _ | - | Reset |
|
||||
| 0 | _ | Set | - |
|
||||
| 0 | _ | Reset | - |
|
||||
| 0 | Yes | - | - |
|
||||
| 1 | Yes | - | Set |
|
||||
| 0 | Yes | - | Reset |
|
||||
| 0 | Yes | Set | - |
|
||||
| 0 | Yes | Reset | - |
|
||||
+-------+--------------+-------------+--------------+
|
||||
|
||||
|
||||
2. Memory
|
||||
---------
|
||||
|
||||
+----------------+------+-------+-----------+-------+
|
||||
| Site Type | Used | Fixed | Available | Util% |
|
||||
+----------------+------+-------+-----------+-------+
|
||||
| Block RAM Tile | 0 | 0 | 50 | 0.00 |
|
||||
| RAMB36/FIFO* | 0 | 0 | 50 | 0.00 |
|
||||
| RAMB18 | 0 | 0 | 100 | 0.00 |
|
||||
+----------------+------+-------+-----------+-------+
|
||||
* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1
|
||||
|
||||
|
||||
3. DSP
|
||||
------
|
||||
|
||||
+-----------+------+-------+-----------+-------+
|
||||
| Site Type | Used | Fixed | Available | Util% |
|
||||
+-----------+------+-------+-----------+-------+
|
||||
| DSPs | 0 | 0 | 90 | 0.00 |
|
||||
+-----------+------+-------+-----------+-------+
|
||||
|
||||
|
||||
4. IO and GT Specific
|
||||
---------------------
|
||||
|
||||
+-----------------------------+------+-------+-----------+-------+
|
||||
| Site Type | Used | Fixed | Available | Util% |
|
||||
+-----------------------------+------+-------+-----------+-------+
|
||||
| Bonded IOB | 18 | 0 | 210 | 8.57 |
|
||||
| Bonded IPADs | 0 | 0 | 2 | 0.00 |
|
||||
| PHY_CONTROL | 0 | 0 | 5 | 0.00 |
|
||||
| PHASER_REF | 0 | 0 | 5 | 0.00 |
|
||||
| OUT_FIFO | 0 | 0 | 20 | 0.00 |
|
||||
| IN_FIFO | 0 | 0 | 20 | 0.00 |
|
||||
| IDELAYCTRL | 0 | 0 | 5 | 0.00 |
|
||||
| IBUFDS | 0 | 0 | 202 | 0.00 |
|
||||
| PHASER_OUT/PHASER_OUT_PHY | 0 | 0 | 20 | 0.00 |
|
||||
| PHASER_IN/PHASER_IN_PHY | 0 | 0 | 20 | 0.00 |
|
||||
| IDELAYE2/IDELAYE2_FINEDELAY | 0 | 0 | 250 | 0.00 |
|
||||
| ILOGIC | 0 | 0 | 210 | 0.00 |
|
||||
| OLOGIC | 0 | 0 | 210 | 0.00 |
|
||||
+-----------------------------+------+-------+-----------+-------+
|
||||
|
||||
|
||||
5. Clocking
|
||||
-----------
|
||||
|
||||
+------------+------+-------+-----------+-------+
|
||||
| Site Type | Used | Fixed | Available | Util% |
|
||||
+------------+------+-------+-----------+-------+
|
||||
| BUFGCTRL | 1 | 0 | 32 | 3.13 |
|
||||
| BUFIO | 0 | 0 | 20 | 0.00 |
|
||||
| MMCME2_ADV | 0 | 0 | 5 | 0.00 |
|
||||
| PLLE2_ADV | 0 | 0 | 5 | 0.00 |
|
||||
| BUFMRCE | 0 | 0 | 10 | 0.00 |
|
||||
| BUFHCE | 0 | 0 | 72 | 0.00 |
|
||||
| BUFR | 0 | 0 | 20 | 0.00 |
|
||||
+------------+------+-------+-----------+-------+
|
||||
|
||||
|
||||
6. Specific Feature
|
||||
-------------------
|
||||
|
||||
+-------------+------+-------+-----------+-------+
|
||||
| Site Type | Used | Fixed | Available | Util% |
|
||||
+-------------+------+-------+-----------+-------+
|
||||
| BSCANE2 | 0 | 0 | 4 | 0.00 |
|
||||
| CAPTUREE2 | 0 | 0 | 1 | 0.00 |
|
||||
| DNA_PORT | 0 | 0 | 1 | 0.00 |
|
||||
| EFUSE_USR | 0 | 0 | 1 | 0.00 |
|
||||
| FRAME_ECCE2 | 0 | 0 | 1 | 0.00 |
|
||||
| ICAPE2 | 0 | 0 | 2 | 0.00 |
|
||||
| PCIE_2_1 | 0 | 0 | 1 | 0.00 |
|
||||
| STARTUPE2 | 0 | 0 | 1 | 0.00 |
|
||||
| XADC | 0 | 0 | 1 | 0.00 |
|
||||
+-------------+------+-------+-----------+-------+
|
||||
|
||||
|
||||
7. Primitives
|
||||
-------------
|
||||
|
||||
+----------+------+---------------------+
|
||||
| Ref Name | Used | Functional Category |
|
||||
+----------+------+---------------------+
|
||||
| OBUF | 16 | IO |
|
||||
| IBUF | 2 | IO |
|
||||
| FDPE | 1 | Flop & Latch |
|
||||
| BUFG | 1 | Clock |
|
||||
+----------+------+---------------------+
|
||||
|
||||
|
||||
8. Black Boxes
|
||||
--------------
|
||||
|
||||
+----------+------+
|
||||
| Ref Name | Used |
|
||||
+----------+------+
|
||||
|
||||
|
||||
9. Instantiated Netlists
|
||||
------------------------
|
||||
|
||||
+----------+------+
|
||||
| Ref Name | Used |
|
||||
+----------+------+
|
||||
|
||||
|
||||
37
Exp8-2/Exp8-2.runs/synth_1/gen_run.xml
Normal file
37
Exp8-2/Exp8-2.runs/synth_1/gen_run.xml
Normal file
@@ -0,0 +1,37 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<GenRun Id="synth_1" LaunchPart="xc7a35tcsg324-1" LaunchTime="1734348038">
|
||||
<File Type="PA-TCL" Name="date_display.tcl"/>
|
||||
<File Type="RDS-PROPCONSTRS" Name="date_display_drc_synth.rpt"/>
|
||||
<File Type="REPORTS-TCL" Name="date_display_reports.tcl"/>
|
||||
<File Type="RDS-RDS" Name="date_display.vds"/>
|
||||
<File Type="RDS-UTIL" Name="date_display_utilization_synth.rpt"/>
|
||||
<File Type="RDS-UTIL-PB" Name="date_display_utilization_synth.pb"/>
|
||||
<File Type="RDS-DCP" Name="date_display.dcp"/>
|
||||
<File Type="VDS-TIMINGSUMMARY" Name="date_display_timing_summary_synth.rpt"/>
|
||||
<File Type="VDS-TIMING-PB" Name="date_display_timing_summary_synth.pb"/>
|
||||
<FileSet Name="sources" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1">
|
||||
<Filter Type="Srcs"/>
|
||||
<File Path="$PSRCDIR/sources_1/new/date_display.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<Config>
|
||||
<Option Name="DesignMode" Val="RTL"/>
|
||||
<Option Name="TopModule" Val="date_display"/>
|
||||
<Option Name="TopAutoSet" Val="TRUE"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="constrs_in" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1">
|
||||
<Filter Type="Constrs"/>
|
||||
<Config>
|
||||
<Option Name="ConstrsType" Val="XDC"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2018"/>
|
||||
<Step Id="synth_design"/>
|
||||
</Strategy>
|
||||
</GenRun>
|
||||
9
Exp8-2/Exp8-2.runs/synth_1/htr.txt
Normal file
9
Exp8-2/Exp8-2.runs/synth_1/htr.txt
Normal file
@@ -0,0 +1,9 @@
|
||||
REM
|
||||
REM Vivado(TM)
|
||||
REM htr.txt: a Vivado-generated description of how-to-repeat the
|
||||
REM the basic steps of a run. Note that runme.bat/sh needs
|
||||
REM to be invoked for Vivado to track run status.
|
||||
REM Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
|
||||
REM
|
||||
|
||||
vivado -log date_display.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source date_display.tcl
|
||||
12
Exp8-2/Exp8-2.runs/synth_1/vivado.jou
Normal file
12
Exp8-2/Exp8-2.runs/synth_1/vivado.jou
Normal file
@@ -0,0 +1,12 @@
|
||||
#-----------------------------------------------------------
|
||||
# Vivado v2018.1 (64-bit)
|
||||
# SW Build 2188600 on Wed Apr 4 18:40:38 MDT 2018
|
||||
# IP Build 2185939 on Wed Apr 4 20:55:05 MDT 2018
|
||||
# Start of session at: Mon Dec 16 19:20:39 2024
|
||||
# Process ID: 20280
|
||||
# Current directory: F:/Schoolwork/DigitalLogic/Exp8-2/Exp8-2.runs/synth_1
|
||||
# Command line: vivado.exe -log date_display.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source date_display.tcl
|
||||
# Log file: F:/Schoolwork/DigitalLogic/Exp8-2/Exp8-2.runs/synth_1/date_display.vds
|
||||
# Journal file: F:/Schoolwork/DigitalLogic/Exp8-2/Exp8-2.runs/synth_1\vivado.jou
|
||||
#-----------------------------------------------------------
|
||||
source date_display.tcl -notrace
|
||||
BIN
Exp8-2/Exp8-2.runs/synth_1/vivado.pb
Normal file
BIN
Exp8-2/Exp8-2.runs/synth_1/vivado.pb
Normal file
Binary file not shown.
Reference in New Issue
Block a user