Initial commit
This commit is contained in:
319
Exp8-2/Exp8-2.runs/synth_1/date_display.vds
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319
Exp8-2/Exp8-2.runs/synth_1/date_display.vds
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#-----------------------------------------------------------
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# Vivado v2018.1 (64-bit)
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# SW Build 2188600 on Wed Apr 4 18:40:38 MDT 2018
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# IP Build 2185939 on Wed Apr 4 20:55:05 MDT 2018
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# Start of session at: Mon Dec 16 19:20:39 2024
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# Process ID: 20280
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# Current directory: F:/Schoolwork/DigitalLogic/Exp8-2/Exp8-2.runs/synth_1
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# Command line: vivado.exe -log date_display.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source date_display.tcl
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# Log file: F:/Schoolwork/DigitalLogic/Exp8-2/Exp8-2.runs/synth_1/date_display.vds
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# Journal file: F:/Schoolwork/DigitalLogic/Exp8-2/Exp8-2.runs/synth_1\vivado.jou
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#-----------------------------------------------------------
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source date_display.tcl -notrace
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Command: synth_design -top date_display -part xc7a35tcsg324-1
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Starting synth_design
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Attempting to get a license for feature 'Synthesis' and/or device 'xc7a35t'
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INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7a35t'
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INFO: Launching helper process for spawning children vivado processes
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INFO: Helper process launched with PID 28272
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---------------------------------------------------------------------------------
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Starting Synthesize : Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 412.238 ; gain = 98.691
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---------------------------------------------------------------------------------
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INFO: [Synth 8-6157] synthesizing module 'date_display' [F:/Schoolwork/DigitalLogic/Exp8-2/Exp8-2.srcs/sources_1/new/date_display.v:23]
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Parameter S0 bound to: 4'b0000
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Parameter S1 bound to: 4'b0001
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Parameter S2 bound to: 4'b0010
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Parameter S3 bound to: 4'b0011
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Parameter S4 bound to: 4'b0100
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Parameter S5 bound to: 4'b0101
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Parameter S6 bound to: 4'b0110
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Parameter S7 bound to: 4'b0111
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Parameter S8 bound to: 4'b1000
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Parameter S9 bound to: 4'b1001
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Parameter S10 bound to: 4'b1010
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Parameter S11 bound to: 4'b1011
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Parameter S12 bound to: 4'b1100
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Parameter S13 bound to: 4'b1101
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Parameter S14 bound to: 4'b1110
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Parameter S15 bound to: 4'b1111
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Parameter SEG_0 bound to: 8'b11111101
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Parameter SEG_1 bound to: 8'b01100001
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Parameter SEG_2 bound to: 8'b11011011
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Parameter SEG_3 bound to: 8'b11110011
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Parameter SEG_4 bound to: 8'b01100111
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Parameter SEG_5 bound to: 8'b10110111
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Parameter SEG_6 bound to: 8'b10111111
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Parameter SEG_7 bound to: 8'b11100001
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Parameter SEG_8 bound to: 8'b11111111
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Parameter SEG_9 bound to: 8'b11110111
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Parameter SEG_DP bound to: 8'b00000001
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INFO: [Synth 8-226] default block is never used [F:/Schoolwork/DigitalLogic/Exp8-2/Exp8-2.srcs/sources_1/new/date_display.v:93]
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WARNING: [Synth 8-6014] Unused sequential element seg_temp_reg was removed. [F:/Schoolwork/DigitalLogic/Exp8-2/Exp8-2.srcs/sources_1/new/date_display.v:121]
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INFO: [Synth 8-6155] done synthesizing module 'date_display' (1#1) [F:/Schoolwork/DigitalLogic/Exp8-2/Exp8-2.srcs/sources_1/new/date_display.v:23]
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---------------------------------------------------------------------------------
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Finished Synthesize : Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 466.418 ; gain = 152.871
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---------------------------------------------------------------------------------
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---------------------------------------------------------------------------------
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Finished Constraint Validation : Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 466.418 ; gain = 152.871
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---------------------------------------------------------------------------------
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---------------------------------------------------------------------------------
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Start Loading Part and Timing Information
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---------------------------------------------------------------------------------
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Loading part: xc7a35tcsg324-1
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---------------------------------------------------------------------------------
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Finished Loading Part and Timing Information : Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 466.418 ; gain = 152.871
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---------------------------------------------------------------------------------
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INFO: [Device 21-403] Loading part xc7a35tcsg324-1
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INFO: [Synth 8-5546] ROM "clk_1hz" won't be mapped to RAM because it is too sparse
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INFO: [Synth 8-5544] ROM "sequence" won't be mapped to Block RAM because address size (4) smaller than threshold (5)
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---------------------------------------------------------------------------------
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Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:04 ; elapsed = 00:00:03 . Memory (MB): peak = 466.418 ; gain = 152.871
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---------------------------------------------------------------------------------
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Report RTL Partitions:
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+-+--------------+------------+----------+
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| |RTL Partition |Replication |Instances |
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+-+--------------+------------+----------+
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+-+--------------+------------+----------+
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No constraint files found.
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---------------------------------------------------------------------------------
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Start RTL Component Statistics
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---------------------------------------------------------------------------------
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Detailed RTL Component Info :
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+---Adders :
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2 Input 20 Bit Adders := 1
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+---Registers :
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20 Bit Registers := 1
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8 Bit Registers := 2
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4 Bit Registers := 1
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1 Bit Registers := 1
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+---Muxes :
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17 Input 56 Bit Muxes := 1
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2 Input 20 Bit Muxes := 1
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2 Input 1 Bit Muxes := 1
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---------------------------------------------------------------------------------
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Finished RTL Component Statistics
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---------------------------------------------------------------------------------
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---------------------------------------------------------------------------------
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Start RTL Hierarchical Component Statistics
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---------------------------------------------------------------------------------
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Hierarchical RTL Component report
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Module date_display
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Detailed RTL Component Info :
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+---Adders :
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2 Input 20 Bit Adders := 1
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+---Registers :
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20 Bit Registers := 1
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8 Bit Registers := 2
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4 Bit Registers := 1
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1 Bit Registers := 1
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+---Muxes :
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17 Input 56 Bit Muxes := 1
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2 Input 20 Bit Muxes := 1
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2 Input 1 Bit Muxes := 1
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---------------------------------------------------------------------------------
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Finished RTL Hierarchical Component Statistics
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---------------------------------------------------------------------------------
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---------------------------------------------------------------------------------
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Start Part Resource Summary
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---------------------------------------------------------------------------------
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Part Resources:
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DSPs: 90 (col length:60)
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BRAMs: 100 (col length: RAMB18 60 RAMB36 30)
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---------------------------------------------------------------------------------
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Finished Part Resource Summary
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---------------------------------------------------------------------------------
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No constraint files found.
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---------------------------------------------------------------------------------
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Start Cross Boundary and Area Optimization
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---------------------------------------------------------------------------------
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Warning: Parallel synthesis criteria is not met
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INFO: [Synth 8-5546] ROM "clk_1hz" won't be mapped to RAM because it is too sparse
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INFO: [Synth 8-3886] merging instance 'an_reg[0]' (FDP) to 'seg_reg[7]'
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INFO: [Synth 8-3886] merging instance 'an_reg[1]' (FDP) to 'an_reg[2]'
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INFO: [Synth 8-3886] merging instance 'an_reg[2]' (FDP) to 'an_reg[3]'
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INFO: [Synth 8-3886] merging instance 'an_reg[3]' (FDP) to 'an_reg[4]'
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INFO: [Synth 8-3886] merging instance 'an_reg[4]' (FDP) to 'an_reg[5]'
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INFO: [Synth 8-3886] merging instance 'an_reg[5]' (FDP) to 'an_reg[6]'
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INFO: [Synth 8-3886] merging instance 'an_reg[6]' (FDP) to 'an_reg[7]'
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INFO: [Synth 8-3333] propagating constant 1 across sequential element (\an_reg[7] )
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INFO: [Synth 8-3886] merging instance 'seg_reg[0]' (FDP) to 'seg_reg[7]'
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INFO: [Synth 8-3886] merging instance 'seg_reg[1]' (FDP) to 'seg_reg[7]'
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INFO: [Synth 8-3886] merging instance 'seg_reg[2]' (FDP) to 'seg_reg[7]'
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INFO: [Synth 8-3886] merging instance 'seg_reg[3]' (FDP) to 'seg_reg[7]'
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INFO: [Synth 8-3886] merging instance 'seg_reg[4]' (FDP) to 'seg_reg[7]'
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INFO: [Synth 8-3886] merging instance 'seg_reg[5]' (FDP) to 'seg_reg[7]'
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INFO: [Synth 8-3886] merging instance 'seg_reg[6]' (FDP) to 'seg_reg[7]'
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WARNING: [Synth 8-3332] Sequential element (state_c_reg_rep[3]) is unused and will be removed from module date_display.
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WARNING: [Synth 8-3332] Sequential element (state_c_reg_rep[2]) is unused and will be removed from module date_display.
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WARNING: [Synth 8-3332] Sequential element (state_c_reg_rep[1]) is unused and will be removed from module date_display.
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WARNING: [Synth 8-3332] Sequential element (state_c_reg_rep[0]) is unused and will be removed from module date_display.
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WARNING: [Synth 8-3332] Sequential element (an_reg[7]) is unused and will be removed from module date_display.
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WARNING: [Synth 8-3332] Sequential element (counter_reg[19]) is unused and will be removed from module date_display.
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WARNING: [Synth 8-3332] Sequential element (counter_reg[18]) is unused and will be removed from module date_display.
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WARNING: [Synth 8-3332] Sequential element (counter_reg[17]) is unused and will be removed from module date_display.
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WARNING: [Synth 8-3332] Sequential element (counter_reg[16]) is unused and will be removed from module date_display.
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WARNING: [Synth 8-3332] Sequential element (counter_reg[15]) is unused and will be removed from module date_display.
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WARNING: [Synth 8-3332] Sequential element (counter_reg[14]) is unused and will be removed from module date_display.
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WARNING: [Synth 8-3332] Sequential element (counter_reg[13]) is unused and will be removed from module date_display.
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WARNING: [Synth 8-3332] Sequential element (counter_reg[12]) is unused and will be removed from module date_display.
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WARNING: [Synth 8-3332] Sequential element (counter_reg[11]) is unused and will be removed from module date_display.
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WARNING: [Synth 8-3332] Sequential element (counter_reg[10]) is unused and will be removed from module date_display.
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WARNING: [Synth 8-3332] Sequential element (counter_reg[9]) is unused and will be removed from module date_display.
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WARNING: [Synth 8-3332] Sequential element (counter_reg[8]) is unused and will be removed from module date_display.
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WARNING: [Synth 8-3332] Sequential element (counter_reg[7]) is unused and will be removed from module date_display.
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WARNING: [Synth 8-3332] Sequential element (counter_reg[6]) is unused and will be removed from module date_display.
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WARNING: [Synth 8-3332] Sequential element (counter_reg[5]) is unused and will be removed from module date_display.
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WARNING: [Synth 8-3332] Sequential element (counter_reg[4]) is unused and will be removed from module date_display.
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WARNING: [Synth 8-3332] Sequential element (counter_reg[3]) is unused and will be removed from module date_display.
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WARNING: [Synth 8-3332] Sequential element (counter_reg[2]) is unused and will be removed from module date_display.
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WARNING: [Synth 8-3332] Sequential element (counter_reg[1]) is unused and will be removed from module date_display.
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WARNING: [Synth 8-3332] Sequential element (counter_reg[0]) is unused and will be removed from module date_display.
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WARNING: [Synth 8-3332] Sequential element (clk_1hz_reg) is unused and will be removed from module date_display.
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WARNING: [Synth 8-3332] Sequential element (state_c_reg[3]) is unused and will be removed from module date_display.
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WARNING: [Synth 8-3332] Sequential element (state_c_reg[2]) is unused and will be removed from module date_display.
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WARNING: [Synth 8-3332] Sequential element (state_c_reg[1]) is unused and will be removed from module date_display.
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WARNING: [Synth 8-3332] Sequential element (state_c_reg[0]) is unused and will be removed from module date_display.
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---------------------------------------------------------------------------------
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Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 586.379 ; gain = 272.832
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---------------------------------------------------------------------------------
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Report RTL Partitions:
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+-+--------------+------------+----------+
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| |RTL Partition |Replication |Instances |
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+-+--------------+------------+----------+
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+-+--------------+------------+----------+
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No constraint files found.
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---------------------------------------------------------------------------------
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Start Timing Optimization
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---------------------------------------------------------------------------------
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---------------------------------------------------------------------------------
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Finished Timing Optimization : Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 586.379 ; gain = 272.832
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---------------------------------------------------------------------------------
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Report RTL Partitions:
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+-+--------------+------------+----------+
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| |RTL Partition |Replication |Instances |
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+-+--------------+------------+----------+
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+-+--------------+------------+----------+
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---------------------------------------------------------------------------------
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Start Technology Mapping
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---------------------------------------------------------------------------------
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---------------------------------------------------------------------------------
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Finished Technology Mapping : Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 586.379 ; gain = 272.832
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---------------------------------------------------------------------------------
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Report RTL Partitions:
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+-+--------------+------------+----------+
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| |RTL Partition |Replication |Instances |
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+-+--------------+------------+----------+
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+-+--------------+------------+----------+
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---------------------------------------------------------------------------------
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Start IO Insertion
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---------------------------------------------------------------------------------
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---------------------------------------------------------------------------------
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Start Flattening Before IO Insertion
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---------------------------------------------------------------------------------
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---------------------------------------------------------------------------------
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Finished Flattening Before IO Insertion
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---------------------------------------------------------------------------------
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---------------------------------------------------------------------------------
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Start Final Netlist Cleanup
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---------------------------------------------------------------------------------
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---------------------------------------------------------------------------------
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Finished Final Netlist Cleanup
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---------------------------------------------------------------------------------
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---------------------------------------------------------------------------------
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Finished IO Insertion : Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 586.379 ; gain = 272.832
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---------------------------------------------------------------------------------
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Report Check Netlist:
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+------+------------------+-------+---------+-------+------------------+
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| |Item |Errors |Warnings |Status |Description |
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+------+------------------+-------+---------+-------+------------------+
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|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets |
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+------+------------------+-------+---------+-------+------------------+
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---------------------------------------------------------------------------------
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Start Renaming Generated Instances
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---------------------------------------------------------------------------------
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---------------------------------------------------------------------------------
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Finished Renaming Generated Instances : Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 586.379 ; gain = 272.832
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---------------------------------------------------------------------------------
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Report RTL Partitions:
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+-+--------------+------------+----------+
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| |RTL Partition |Replication |Instances |
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+-+--------------+------------+----------+
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+-+--------------+------------+----------+
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---------------------------------------------------------------------------------
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Start Rebuilding User Hierarchy
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---------------------------------------------------------------------------------
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---------------------------------------------------------------------------------
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Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 586.379 ; gain = 272.832
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---------------------------------------------------------------------------------
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---------------------------------------------------------------------------------
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Start Renaming Generated Ports
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---------------------------------------------------------------------------------
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---------------------------------------------------------------------------------
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Finished Renaming Generated Ports : Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 586.379 ; gain = 272.832
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---------------------------------------------------------------------------------
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---------------------------------------------------------------------------------
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Start Handling Custom Attributes
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---------------------------------------------------------------------------------
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---------------------------------------------------------------------------------
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Finished Handling Custom Attributes : Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 586.379 ; gain = 272.832
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---------------------------------------------------------------------------------
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---------------------------------------------------------------------------------
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Start Renaming Generated Nets
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---------------------------------------------------------------------------------
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---------------------------------------------------------------------------------
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Finished Renaming Generated Nets : Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 586.379 ; gain = 272.832
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---------------------------------------------------------------------------------
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---------------------------------------------------------------------------------
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Start Writing Synthesis Report
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---------------------------------------------------------------------------------
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Report BlackBoxes:
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+-+--------------+----------+
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| |BlackBox name |Instances |
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+-+--------------+----------+
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+-+--------------+----------+
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Report Cell Usage:
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+------+-----+------+
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| |Cell |Count |
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+------+-----+------+
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|1 |BUFG | 1|
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|2 |FDPE | 1|
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|3 |IBUF | 2|
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|4 |OBUF | 16|
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+------+-----+------+
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Report Instance Areas:
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+------+---------+-------+------+
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| |Instance |Module |Cells |
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+------+---------+-------+------+
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|1 |top | | 20|
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+------+---------+-------+------+
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---------------------------------------------------------------------------------
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Finished Writing Synthesis Report : Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 586.379 ; gain = 272.832
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---------------------------------------------------------------------------------
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Synthesis finished with 0 errors, 0 critical warnings and 31 warnings.
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Synthesis Optimization Runtime : Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 586.379 ; gain = 272.832
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Synthesis Optimization Complete : Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 586.379 ; gain = 272.832
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INFO: [Project 1-571] Translating synthesized netlist
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INFO: [Netlist 29-17] Analyzing 2 Unisim elements for replacement
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INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
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INFO: [Project 1-570] Preparing netlist for logic optimization
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INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
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INFO: [Project 1-111] Unisim Transformation Summary:
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No Unisim elements were transformed.
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INFO: [Common 17-83] Releasing license: Synthesis
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30 Infos, 31 Warnings, 0 Critical Warnings and 0 Errors encountered.
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synth_design completed successfully
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synth_design: Time (s): cpu = 00:00:08 ; elapsed = 00:00:10 . Memory (MB): peak = 692.234 ; gain = 391.566
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INFO: [Common 17-1381] The checkpoint 'F:/Schoolwork/DigitalLogic/Exp8-2/Exp8-2.runs/synth_1/date_display.dcp' has been generated.
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INFO: [runtcl-4] Executing : report_utilization -file date_display_utilization_synth.rpt -pb date_display_utilization_synth.pb
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report_utilization: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.011 . Memory (MB): peak = 692.234 ; gain = 0.000
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INFO: [Common 17-206] Exiting Vivado at Mon Dec 16 19:20:53 2024...
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Reference in New Issue
Block a user