Initial commit

2025-11-06 10:08:01 +08:00
commit 0bded5b86e
1033 changed files with 55966 additions and 0 deletions
--- a/Exp8-2/Exp8-2.srcs/sources_1/new/date_display.v
+++ b/Exp8-2/Exp8-2.srcs/sources_1/new/date_display.v
@@ -0,0 +1,127 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date: 2024/12/16 18:24:15
+// Design Name: 
+// Module Name: date_display
+// Project Name: 
+// Target Devices: 
+// Tool Versions: 
+// Description: 
+// 
+// Dependencies: 
+// 
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+// 
+//////////////////////////////////////////////////////////////////////////////////
+
+
+module date_display (
+    input wire clk,          // 100 MHz clock input
+    input wire reset,        // Reset signal
+    output reg [7:0] seg,    // Segment control for 7-segment display
+    output reg [7:0] an      // Anode control for dynamic display
+);
+
+// State definitions
+parameter S0  = 4'd0, S1  = 4'd1, S2  = 4'd2, S3  = 4'd3,
+          S4  = 4'd4, S5  = 4'd5, S6  = 4'd6, S7  = 4'd7,
+          S8  = 4'd8, S9  = 4'd9, S10 = 4'd10, S11 = 4'd11,
+          S12 = 4'd12, S13 = 4'd13, S14 = 4'd14, S15 = 4'd15;
+
+reg [3:0] state_c, state_n; // Current state and next state
+reg [19:0] counter;         // Counter for clock division
+reg clk_1hz;                // 1 Hz clock
+
+// Segment encoding with dot (decimal point)
+parameter [7:0] SEG_0 = 8'b11111101, SEG_1 = 8'b01100001, SEG_2 = 8'b11011011,
+                SEG_3 = 8'b11110011, SEG_4 = 8'b01100111, SEG_5 = 8'b10110111,
+                SEG_6 = 8'b10111111, SEG_7 = 8'b11100001, SEG_8 = 8'b11111111,
+                SEG_9 = 8'b11110111, SEG_DP = 8'b00000001;
+
+// Time sequence for display
+reg [55:0] sequence [15:0];
+initial begin
+    sequence[S0]  = 56'b00000000_00000000_00000000_00000000_00000000_11111101; // 2
+    sequence[S1]  = 56'b00000000_00000000_00000000_00000000_00000011_01100001; // 20
+    sequence[S2]  = 56'b00000000_00000000_00000000_00000000_11011011_11110011; // 202
+    sequence[S3]  = 56'b00000000_00000000_00000000_00000001_11011011_01100001; // 2024.
+    sequence[S4]  = 56'b00000000_00000000_00000000_00001101_10110111_11011011; // 2024.1
+    sequence[S5]  = 56'b00000000_00000000_00000110_11011011_10111111_10110111; // 2024.12.
+    sequence[S6]  = 56'b00000000_00000000_00001100_11100001_11110011_01100001; // 2024.12.1
+    sequence[S7]  = 56'b00000000_00000000_11100001_10111111_11011011_11011011; // 2024.12.16
+    sequence[S8]  = 56'b00000000_00000001_11011011_11011011_11011011_10110111; // 024.12.16
+    sequence[S9]  = 56'b00000000_00000110_01100001_11100001_11110011_10111111; // 24.12.16
+    sequence[S10] = 56'b00000000_00001111_11110111_11111111_01100001_10111111; // 4.12.16
+    sequence[S11] = 56'b00000000_11111111_11111111_01100111_11111101_01100001; // 12.16
+    sequence[S12] = 56'b11111101_01100001_11111101_01100001_11110111_01100111; // 2.16
+    sequence[S13] = 56'b11110111_11111101_11111111_01100001_01100001_01100001; // 16
+    sequence[S14] = 56'b00000000_11111101_01100001_00000000_00000000_00000000; // 6
+    sequence[S15] = 56'b00000000_00000000_00000000_00000000_00000000_00000000; // Blank
+end
+
+// Clock division to generate 1 Hz clock
+always @(posedge clk or posedge reset) begin
+    if (reset) begin
+        counter <= 0;
+        clk_1hz <= 0;
+    end else begin
+        if (counter == 20'd999_999) begin
+            clk_1hz <= ~clk_1hz;
+            counter <= 0;
+        end else begin
+            counter <= counter + 1;
+        end
+    end
+end
+
+// State transition logic
+always @(posedge clk_1hz or posedge reset) begin
+    if (reset) begin
+        state_c <= S0;
+    end else begin
+        state_c <= state_n;
+    end
+end
+
+// Next state logic
+always @(*) begin
+    case (state_c)
+        S0: state_n = S1;
+        S1: state_n = S2;
+        S2: state_n = S3;
+        S3: state_n = S4;
+        S4: state_n = S5;
+        S5: state_n = S6;
+        S6: state_n = S7;
+        S7: state_n = S8;
+        S8: state_n = S9;
+        S9: state_n = S10;
+        S10: state_n = S11;
+        S11: state_n = S12;
+        S12: state_n = S13;
+        S13: state_n = S14;
+        S14: state_n = S15;
+        S15: state_n = S0;
+        default: state_n = S0;
+    endcase
+end
+
+// Output logic for 7-segment display
+reg [7:0] seg_temp;
+always @(posedge clk or posedge reset) begin
+    if (reset) begin
+        seg <= 8'b11111111;
+        an <= 8'b11111111;
+    end else begin
+        seg_temp = sequence[state_c][55:48];
+        an <= 8'b11111110; // Activate only one digit (dynamic display)
+        seg <= seg_temp;
+    end
+end
+
+endmodule