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2025-11-06 10:08:01 +08:00
commit 0bded5b86e
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8
test/test.runs/.jobs/vrs_config_1.xml Normal file
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<?xml version="1.0"?>
<Runs Version="1" Minor="0">
<Run Id="synth_1" LaunchDir="E:/Schoolwork/DigitalLogic/test/test.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
<Run Id="impl_1" LaunchDir="E:/Schoolwork/DigitalLogic/test/test.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="init_design" ToStepId="write_bitstream">
<Parent Id="synth_1"/>
</Run>
</Runs>

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test/test.runs/.jobs/vrs_config_10.xml Normal file
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<?xml version="1.0"?>
<Runs Version="1" Minor="0">
<Run Id="synth_1" LaunchDir="Z:/Storage/Schoolwork/DigitalLogic/test/test.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
<Run Id="impl_1" LaunchDir="Z:/Storage/Schoolwork/DigitalLogic/test/test.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="init_design" ToStepId="write_bitstream">
<Parent Id="synth_1"/>
</Run>
</Runs>

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test/test.runs/.jobs/vrs_config_2.xml Normal file
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<?xml version="1.0"?>
<Runs Version="1" Minor="0">
<Run Id="synth_1" LaunchDir="E:/Schoolwork/DigitalLogic/test/test.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
<Run Id="impl_1" LaunchDir="E:/Schoolwork/DigitalLogic/test/test.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="init_design" ToStepId="write_bitstream">
<Parent Id="synth_1"/>
</Run>
</Runs>

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test/test.runs/.jobs/vrs_config_3.xml Normal file
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<?xml version="1.0"?>
<Runs Version="1" Minor="0">
<Run Id="synth_1" LaunchDir="Z:/Storage/Schoolwork/DigitalLogic/test/test.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
<Run Id="impl_1" LaunchDir="Z:/Storage/Schoolwork/DigitalLogic/test/test.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="init_design" ToStepId="write_bitstream">
<Parent Id="synth_1"/>
</Run>
</Runs>

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test/test.runs/.jobs/vrs_config_4.xml Normal file
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<?xml version="1.0"?>
<Runs Version="1" Minor="0">
<Run Id="synth_1" LaunchDir="Z:/Storage/Schoolwork/DigitalLogic/test/test.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
<Run Id="impl_1" LaunchDir="Z:/Storage/Schoolwork/DigitalLogic/test/test.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="init_design" ToStepId="write_bitstream">
<Parent Id="synth_1"/>
</Run>
</Runs>

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test/test.runs/.jobs/vrs_config_5.xml Normal file
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<?xml version="1.0"?>
<Runs Version="1" Minor="0">
<Run Id="synth_1" LaunchDir="Z:/Storage/Schoolwork/DigitalLogic/test/test.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
<Run Id="impl_1" LaunchDir="Z:/Storage/Schoolwork/DigitalLogic/test/test.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="init_design" ToStepId="write_bitstream">
<Parent Id="synth_1"/>
</Run>
</Runs>

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test/test.runs/.jobs/vrs_config_6.xml Normal file
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<?xml version="1.0"?>
<Runs Version="1" Minor="0">
<Run Id="synth_1" LaunchDir="Z:/Storage/Schoolwork/DigitalLogic/test/test.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
<Run Id="impl_1" LaunchDir="Z:/Storage/Schoolwork/DigitalLogic/test/test.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="init_design" ToStepId="write_bitstream">
<Parent Id="synth_1"/>
</Run>
</Runs>

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test/test.runs/.jobs/vrs_config_7.xml Normal file
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<?xml version="1.0"?>
<Runs Version="1" Minor="0">
<Run Id="synth_1" LaunchDir="Z:/Storage/Schoolwork/DigitalLogic/test/test.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
<Run Id="impl_1" LaunchDir="Z:/Storage/Schoolwork/DigitalLogic/test/test.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="init_design" ToStepId="write_bitstream">
<Parent Id="synth_1"/>
</Run>
</Runs>

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test/test.runs/.jobs/vrs_config_8.xml Normal file
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<?xml version="1.0"?>
<Runs Version="1" Minor="0">
<Run Id="synth_1" LaunchDir="Z:/Storage/Schoolwork/DigitalLogic/test/test.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
<Run Id="impl_1" LaunchDir="Z:/Storage/Schoolwork/DigitalLogic/test/test.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="init_design" ToStepId="write_bitstream">
<Parent Id="synth_1"/>
</Run>
</Runs>

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test/test.runs/.jobs/vrs_config_9.xml Normal file
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<?xml version="1.0"?>
<Runs Version="1" Minor="0">
<Run Id="synth_1" LaunchDir="Z:/Storage/Schoolwork/DigitalLogic/test/test.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
<Run Id="impl_1" LaunchDir="Z:/Storage/Schoolwork/DigitalLogic/test/test.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="init_design" ToStepId="write_bitstream">
<Parent Id="synth_1"/>
</Run>
</Runs>

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test/test.runs/impl_1/gen_run.xml Normal file
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<?xml version="1.0" encoding="UTF-8"?>
<GenRun Id="impl_1" LaunchPart="xc7a35tcsg324-1" LaunchTime="1734550937">
<File Type="PWROPT-DCP" Name="t_date_pwropt.dcp"/>
<File Type="ROUTE-PWR" Name="t_date_power_routed.rpt"/>
<File Type="PA-TCL" Name="t_date.tcl"/>
<File Type="ROUTE-PWR-SUM" Name="t_date_power_summary_routed.pb"/>
<File Type="REPORTS-TCL" Name="t_date_reports.tcl"/>
<File Type="BG-DRC" Name="t_date.drc"/>
<File Type="OPT-METHODOLOGY-DRC" Name="t_date_methodology_drc_opted.rpt"/>
<File Type="INIT-TIMING" Name="t_date_timing_summary_init.rpt"/>
<File Type="OPT-HWDEF" Name="t_date.hwdef"/>
<File Type="OPT-DCP" Name="t_date_opt.dcp"/>
<File Type="OPT-DRC" Name="t_date_drc_opted.rpt"/>
<File Type="OPT-TIMING" Name="t_date_timing_summary_opted.rpt"/>
<File Type="PWROPT-DRC" Name="t_date_drc_pwropted.rpt"/>
<File Type="PWROPT-TIMING" Name="t_date_timing_summary_pwropted.rpt"/>
<File Type="PLACE-DCP" Name="t_date_placed.dcp"/>
<File Type="PLACE-IO" Name="t_date_io_placed.rpt"/>
<File Type="PLACE-CLK" Name="t_date_clock_utilization_placed.rpt"/>
<File Type="PLACE-UTIL" Name="t_date_utilization_placed.rpt"/>
<File Type="PLACE-UTIL-PB" Name="t_date_utilization_placed.pb"/>
<File Type="PLACE-CTRL" Name="t_date_control_sets_placed.rpt"/>
<File Type="PLACE-SIMILARITY" Name="t_date_incremental_reuse_placed.rpt"/>
<File Type="PLACE-PRE-SIMILARITY" Name="t_date_incremental_reuse_pre_placed.rpt"/>
<File Type="PLACE-TIMING" Name="t_date_timing_summary_placed.rpt"/>
<File Type="POSTPLACE-PWROPT-DCP" Name="t_date_postplace_pwropt.dcp"/>
<File Type="POSTPLACE-PWROPT-TIMING" Name="t_date_timing_summary_postplace_pwropted.rpt"/>
<File Type="PHYSOPT-DCP" Name="t_date_physopt.dcp"/>
<File Type="PHYSOPT-DRC" Name="t_date_drc_physopted.rpt"/>
<File Type="BG-BIT" Name="t_date.bit"/>
<File Type="PHYSOPT-TIMING" Name="t_date_timing_summary_physopted.rpt"/>
<File Type="ROUTE-ERROR-DCP" Name="t_date_routed_error.dcp"/>
<File Type="ROUTE-DCP" Name="t_date_routed.dcp"/>
<File Type="ROUTE-BLACKBOX-DCP" Name="t_date_routed_bb.dcp"/>
<File Type="ROUTE-DRC" Name="t_date_drc_routed.rpt"/>
<File Type="ROUTE-DRC-PB" Name="t_date_drc_routed.pb"/>
<File Type="BITSTR-MSK" Name="t_date.msk"/>
<File Type="ROUTE-DRC-RPX" Name="t_date_drc_routed.rpx"/>
<File Type="BG-BGN" Name="t_date.bgn"/>
<File Type="ROUTE-METHODOLOGY-DRC" Name="t_date_methodology_drc_routed.rpt"/>
<File Type="BITSTR-RBT" Name="t_date.rbt"/>
<File Type="ROUTE-METHODOLOGY-DRC-RPX" Name="t_date_methodology_drc_routed.rpx"/>
<File Type="BG-BIN" Name="t_date.bin"/>
<File Type="ROUTE-METHODOLOGY-DRC-PB" Name="t_date_methodology_drc_routed.pb"/>
<File Type="ROUTE-PWR-RPX" Name="t_date_power_routed.rpx"/>
<File Type="ROUTE-STATUS" Name="t_date_route_status.rpt"/>
<File Type="ROUTE-STATUS-PB" Name="t_date_route_status.pb"/>
<File Type="ROUTE-TIMINGSUMMARY" Name="t_date_timing_summary_routed.rpt"/>
<File Type="ROUTE-TIMING-PB" Name="t_date_timing_summary_routed.pb"/>
<File Type="ROUTE-TIMING-RPX" Name="t_date_timing_summary_routed.rpx"/>
<File Type="ROUTE-SIMILARITY" Name="t_date_incremental_reuse_routed.rpt"/>
<File Type="RDI-RDI" Name="t_date.vdi"/>
<File Type="ROUTE-CLK" Name="t_date_clock_utilization_routed.rpt"/>
<File Type="POSTROUTE-PHYSOPT-DCP" Name="t_date_postroute_physopt.dcp"/>
<File Type="POSTROUTE-PHYSOPT-BLACKBOX-DCP" Name="t_date_postroute_physopt_bb.dcp"/>
<File Type="POSTROUTE-PHYSOPT-TIMING" Name="t_date_timing_summary_postroute_physopted.rpt"/>
<File Type="POSTROUTE-PHYSOPT-TIMING-PB" Name="t_date_timing_summary_postroute_physopted.pb"/>
<File Type="POSTROUTE-PHYSOPT-TIMING-RPX" Name="t_date_timing_summary_postroute_physopted.rpx"/>
<File Type="BITSTR-NKY" Name="t_date.nky"/>
<File Type="BITSTR-BMM" Name="t_date_bd.bmm"/>
<File Type="BITSTR-MMI" Name="t_date.mmi"/>
<File Type="BITSTR-LTX" Name="debug_nets.ltx"/>
<File Type="BITSTR-LTX" Name="t_date.ltx"/>
<File Type="BITSTR-SYSDEF" Name="t_date.sysdef"/>
<File Type="WBT-USG" Name="usage_statistics_webtalk.html"/>
<FileSet Name="sources" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1">
<Filter Type="Srcs"/>
<File Path="$PSRCDIR/sources_1/imports/Downloads/slow.v">
<FileInfo>
<Attr Name="ImportPath" Val="$PPRDIR/../../../Downloads/slow.v"/>
<Attr Name="ImportTime" Val="1734532876"/>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/imports/Downloads/t_date.v">
<FileInfo>
<Attr Name="ImportPath" Val="$PPRDIR/../../../Downloads/t_date.v"/>
<Attr Name="ImportTime" Val="1734443575"/>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/imports/Downloads/OUT.v">
<FileInfo>
<Attr Name="AutoDisabled" Val="1"/>
<Attr Name="ImportPath" Val="$PPRDIR/../../../Downloads/OUT.v"/>
<Attr Name="ImportTime" Val="1734532870"/>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<Config>
<Option Name="DesignMode" Val="RTL"/>
<Option Name="TopModule" Val="t_date"/>
<Option Name="TopAutoSet" Val="TRUE"/>
</Config>
</FileSet>
<FileSet Name="constrs_in" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1">
<Filter Type="Constrs"/>
<File Path="$PSRCDIR/constrs_1/imports/Downloads/EX1.xdc">
<FileInfo>
<Attr Name="ImportPath" Val="$PPRDIR/../../../Downloads/EX1.xdc"/>
<Attr Name="ImportTime" Val="1734529765"/>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
</FileInfo>
</File>
<Config>
<Option Name="ConstrsType" Val="XDC"/>
</Config>
</FileSet>
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2018"/>
<Step Id="init_design"/>
<Step Id="opt_design"/>
<Step Id="power_opt_design"/>
<Step Id="place_design"/>
<Step Id="post_place_power_opt_design"/>
<Step Id="phys_opt_design"/>
<Step Id="route_design"/>
<Step Id="post_route_phys_opt_design"/>
<Step Id="write_bitstream"/>
</Strategy>
</GenRun>

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test/test.runs/impl_1/htr.txt Normal file
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REM
REM Vivado(TM)
REM htr.txt: a Vivado-generated description of how-to-repeat the
REM the basic steps of a run. Note that runme.bat/sh needs
REM to be invoked for Vivado to track run status.
REM Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
REM
vivado -log t_date.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source t_date.tcl -notrace

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test/test.runs/impl_1/route_report_bus_skew_0.rpt Normal file
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Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
-----------------------------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2018.1 (win64) Build 2188600 Wed Apr 4 18:40:38 MDT 2018
| Date : Thu Dec 19 03:43:36 2024
| Host : WIN-P8FUKGQFPK3 running 64-bit major release (build 9200)
| Command : report_bus_skew -warn_on_violation -file route_report_bus_skew_0.rpt -rpx route_report_bus_skew_0.rpx
| Design : t_date
| Device : 7a35t-csg324
| Speed File : -1 PRODUCTION 1.21 2018-02-08
-----------------------------------------------------------------------------------------------------------------------
Bus Skew Report
No bus skew constraints

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test/test.runs/impl_1/t_date.tcl Normal file
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#
# Report generation script generated by Vivado
#
proc create_report { reportName command } {
set status "."
append status $reportName ".fail"
if { [file exists $status] } {
eval file delete [glob $status]
}
send_msg_id runtcl-4 info "Executing : $command"
set retval [eval catch { $command } msg]
if { $retval != 0 } {
set fp [open $status w]
close $fp
send_msg_id runtcl-5 warning "$msg"
}
}
proc start_step { step } {
set stopFile ".stop.rst"
if {[file isfile .stop.rst]} {
puts ""
puts "*** Halting run - EA reset detected ***"
puts ""
puts ""
return -code error
}
set beginFile ".$step.begin.rst"
set platform "$::tcl_platform(platform)"
set user "$::tcl_platform(user)"
set pid [pid]
set host ""
if { [string equal $platform unix] } {
if { [info exist ::env(HOSTNAME)] } {
set host $::env(HOSTNAME)
}
} else {
if { [info exist ::env(COMPUTERNAME)] } {
set host $::env(COMPUTERNAME)
}
}
set ch [open $beginFile w]
puts $ch "<?xml version=\"1.0\"?>"
puts $ch "<ProcessHandle Version=\"1\" Minor=\"0\">"
puts $ch " <Process Command=\".planAhead.\" Owner=\"$user\" Host=\"$host\" Pid=\"$pid\">"
puts $ch " </Process>"
puts $ch "</ProcessHandle>"
close $ch
}
proc end_step { step } {
set endFile ".$step.end.rst"
set ch [open $endFile w]
close $ch
}
proc step_failed { step } {
set endFile ".$step.error.rst"
set ch [open $endFile w]
close $ch
}
start_step init_design
set ACTIVE_STEP init_design
set rc [catch {
create_msg_db init_design.pb
set_param xicom.use_bs_reader 1
create_project -in_memory -part xc7a35tcsg324-1
set_property design_mode GateLvl [current_fileset]
set_param project.singleFileAddWarning.threshold 0
set_property webtalk.parent_dir Z:/Storage/Schoolwork/DigitalLogic/test/test.cache/wt [current_project]
set_property parent.project_path Z:/Storage/Schoolwork/DigitalLogic/test/test.xpr [current_project]
set_property ip_output_repo Z:/Storage/Schoolwork/DigitalLogic/test/test.cache/ip [current_project]
set_property ip_cache_permissions {read write} [current_project]
add_files -quiet Z:/Storage/Schoolwork/DigitalLogic/test/test.runs/synth_1/t_date.dcp
read_xdc Z:/Storage/Schoolwork/DigitalLogic/test/test.srcs/constrs_1/imports/Downloads/EX1.xdc
link_design -top t_date -part xc7a35tcsg324-1
close_msg_db -file init_design.pb
} RESULT]
if {$rc} {
step_failed init_design
return -code error $RESULT
} else {
end_step init_design
unset ACTIVE_STEP
}
start_step opt_design
set ACTIVE_STEP opt_design
set rc [catch {
create_msg_db opt_design.pb
opt_design
write_checkpoint -force t_date_opt.dcp
create_report "impl_1_opt_report_drc_0" "report_drc -file t_date_drc_opted.rpt -pb t_date_drc_opted.pb -rpx t_date_drc_opted.rpx"
close_msg_db -file opt_design.pb
} RESULT]
if {$rc} {
step_failed opt_design
return -code error $RESULT
} else {
end_step opt_design
unset ACTIVE_STEP
}
start_step place_design
set ACTIVE_STEP place_design
set rc [catch {
create_msg_db place_design.pb
if { [llength [get_debug_cores -quiet] ] > 0 } {
implement_debug_core
}
place_design
write_checkpoint -force t_date_placed.dcp
create_report "impl_1_place_report_io_0" "report_io -file t_date_io_placed.rpt"
create_report "impl_1_place_report_utilization_0" "report_utilization -file t_date_utilization_placed.rpt -pb t_date_utilization_placed.pb"
create_report "impl_1_place_report_control_sets_0" "report_control_sets -verbose -file t_date_control_sets_placed.rpt"
close_msg_db -file place_design.pb
} RESULT]
if {$rc} {
step_failed place_design
return -code error $RESULT
} else {
end_step place_design
unset ACTIVE_STEP
}
start_step route_design
set ACTIVE_STEP route_design
set rc [catch {
create_msg_db route_design.pb
route_design
write_checkpoint -force t_date_routed.dcp
create_report "impl_1_route_report_drc_0" "report_drc -file t_date_drc_routed.rpt -pb t_date_drc_routed.pb -rpx t_date_drc_routed.rpx"
create_report "impl_1_route_report_methodology_0" "report_methodology -file t_date_methodology_drc_routed.rpt -pb t_date_methodology_drc_routed.pb -rpx t_date_methodology_drc_routed.rpx"
create_report "impl_1_route_report_power_0" "report_power -file t_date_power_routed.rpt -pb t_date_power_summary_routed.pb -rpx t_date_power_routed.rpx"
create_report "impl_1_route_report_route_status_0" "report_route_status -file t_date_route_status.rpt -pb t_date_route_status.pb"
create_report "impl_1_route_report_timing_summary_0" "report_timing_summary -max_paths 10 -file t_date_timing_summary_routed.rpt -pb t_date_timing_summary_routed.pb -rpx t_date_timing_summary_routed.rpx -warn_on_violation "
create_report "impl_1_route_report_incremental_reuse_0" "report_incremental_reuse -file t_date_incremental_reuse_routed.rpt"
create_report "impl_1_route_report_clock_utilization_0" "report_clock_utilization -file t_date_clock_utilization_routed.rpt"
create_report "impl_1_route_report_bus_skew_0" "report_bus_skew -warn_on_violation -file route_report_bus_skew_0.rpt -rpx route_report_bus_skew_0.rpx"
close_msg_db -file route_design.pb
} RESULT]
if {$rc} {
write_checkpoint -force t_date_routed_error.dcp
step_failed route_design
return -code error $RESULT
} else {
end_step route_design
unset ACTIVE_STEP
}
start_step write_bitstream
set ACTIVE_STEP write_bitstream
set rc [catch {
create_msg_db write_bitstream.pb
catch { write_mem_info -force t_date.mmi }
write_bitstream -force t_date.bit
catch {write_debug_probes -quiet -force t_date}
catch {file copy -force t_date.ltx debug_nets.ltx}
close_msg_db -file write_bitstream.pb
} RESULT]
if {$rc} {
step_failed write_bitstream
return -code error $RESULT
} else {
end_step write_bitstream
unset ACTIVE_STEP
}

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test/test.runs/impl_1/t_date.vdi Normal file
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#-----------------------------------------------------------
# Vivado v2018.1 (64-bit)
# SW Build 2188600 on Wed Apr 4 18:40:38 MDT 2018
# IP Build 2185939 on Wed Apr 4 20:55:05 MDT 2018
# Start of session at: Thu Dec 19 03:42:56 2024
# Process ID: 4648
# Current directory: Z:/Storage/Schoolwork/DigitalLogic/test/test.runs/impl_1
# Command line: vivado.exe -log t_date.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source t_date.tcl -notrace
# Log file: Z:/Storage/Schoolwork/DigitalLogic/test/test.runs/impl_1/t_date.vdi
# Journal file: Z:/Storage/Schoolwork/DigitalLogic/test/test.runs/impl_1\vivado.jou
#-----------------------------------------------------------
source t_date.tcl -notrace
Command: link_design -top t_date -part xc7a35tcsg324-1
Design is defaulting to srcset: sources_1
Design is defaulting to constrset: constrs_1
INFO: [Netlist 29-17] Analyzing 12 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
INFO: [Project 1-479] Netlist was created with Vivado 2018.1
INFO: [Device 21-403] Loading part xc7a35tcsg324-1
INFO: [Project 1-570] Preparing netlist for logic optimization
Parsing XDC File [Z:/Storage/Schoolwork/DigitalLogic/test/test.srcs/constrs_1/imports/Downloads/EX1.xdc]
Finished Parsing XDC File [Z:/Storage/Schoolwork/DigitalLogic/test/test.srcs/constrs_1/imports/Downloads/EX1.xdc]
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
INFO: [Project 1-111] Unisim Transformation Summary:
No Unisim elements were transformed.
7 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
link_design completed successfully
link_design: Time (s): cpu = 00:00:02 ; elapsed = 00:00:06 . Memory (MB): peak = 607.418 ; gain = 303.824
Command: opt_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t'
Running DRC as a precondition to command opt_design
Starting DRC Task
INFO: [DRC 23-27] Running DRC with 2 threads
INFO: [Project 1-461] DRC finished with 0 Errors
INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information.
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.400 . Memory (MB): peak = 620.312 ; gain = 12.895
INFO: [Timing 38-35] Done setting XDC timing constraints.
Starting Logic Optimization Task
Phase 1 Retarget
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
INFO: [Opt 31-49] Retargeted 0 cell(s).
Phase 1 Retarget | Checksum: 18d814d52
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.014 . Memory (MB): peak = 1176.613 ; gain = 0.000
INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 0 cells
Phase 2 Constant propagation
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
Phase 2 Constant propagation | Checksum: 18d814d52
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.019 . Memory (MB): peak = 1176.613 ; gain = 0.000
INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells
Phase 3 Sweep
Phase 3 Sweep | Checksum: 17c495346
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.026 . Memory (MB): peak = 1176.613 ; gain = 0.000
INFO: [Opt 31-389] Phase Sweep created 4 cells and removed 0 cells
Phase 4 BUFG optimization
Phase 4 BUFG optimization | Checksum: 17c495346
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.031 . Memory (MB): peak = 1176.613 ; gain = 0.000
INFO: [Opt 31-389] Phase BUFG optimization created 0 cells and removed 0 cells
Phase 5 Shift Register Optimization
Phase 5 Shift Register Optimization | Checksum: 17c495346
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.034 . Memory (MB): peak = 1176.613 ; gain = 0.000
INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells
Phase 6 Post Processing Netlist
Phase 6 Post Processing Netlist | Checksum: 17c495346
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.037 . Memory (MB): peak = 1176.613 ; gain = 0.000
INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells
Starting Connectivity Check Task
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.002 . Memory (MB): peak = 1176.613 ; gain = 0.000
Ending Logic Optimization Task | Checksum: 17c495346
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.041 . Memory (MB): peak = 1176.613 ; gain = 0.000
Starting Power Optimization Task
INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns.
Ending Power Optimization Task | Checksum: 1aa1fde4e
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.008 . Memory (MB): peak = 1176.613 ; gain = 0.000
INFO: [Common 17-83] Releasing license: Implementation
23 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
opt_design completed successfully
opt_design: Time (s): cpu = 00:00:05 ; elapsed = 00:00:10 . Memory (MB): peak = 1176.613 ; gain = 569.195
INFO: [Timing 38-480] Writing timing data to binary archive.
Writing placer database...
Writing XDEF routing.
Writing XDEF routing logical nets.
Writing XDEF routing special nets.
Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.066 . Memory (MB): peak = 1176.613 ; gain = 0.000
INFO: [Common 17-1381] The checkpoint 'Z:/Storage/Schoolwork/DigitalLogic/test/test.runs/impl_1/t_date_opt.dcp' has been generated.
INFO: [runtcl-4] Executing : report_drc -file t_date_drc_opted.rpt -pb t_date_drc_opted.pb -rpx t_date_drc_opted.rpx
Command: report_drc -file t_date_drc_opted.rpt -pb t_date_drc_opted.pb -rpx t_date_drc_opted.rpx
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'C:/Xilinx/Vivado/2018.1/data/ip'.
INFO: [DRC 23-27] Running DRC with 2 threads
INFO: [Coretcl 2-168] The results of DRC are in file Z:/Storage/Schoolwork/DigitalLogic/test/test.runs/impl_1/t_date_drc_opted.rpt.
report_drc completed successfully
Command: place_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t'
INFO: [DRC 23-27] Running DRC with 2 threads
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
Running DRC as a precondition to command place_design
INFO: [DRC 23-27] Running DRC with 2 threads
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
Starting Placer Task
INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 2 CPUs
Phase 1 Placer Initialization
Phase 1.1 Placer Initialization Netlist Sorting
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1176.613 ; gain = 0.000
Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 11bcdb05b
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.007 . Memory (MB): peak = 1176.613 ; gain = 0.000
INFO: [Timing 38-35] Done setting XDC timing constraints.
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1186.355 ; gain = 0.000
Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device
INFO: [Timing 38-35] Done setting XDC timing constraints.
Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 132ecb1d1
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.428 . Memory (MB): peak = 1186.641 ; gain = 10.027
Phase 1.3 Build Placer Netlist Model
Phase 1.3 Build Placer Netlist Model | Checksum: 1e29ea11a
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.444 . Memory (MB): peak = 1186.641 ; gain = 10.027
Phase 1.4 Constrain Clocks/Macros
Phase 1.4 Constrain Clocks/Macros | Checksum: 1e29ea11a
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.447 . Memory (MB): peak = 1186.641 ; gain = 10.027
Phase 1 Placer Initialization | Checksum: 1e29ea11a
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.448 . Memory (MB): peak = 1186.641 ; gain = 10.027
Phase 2 Global Placement
Phase 2 Global Placement | Checksum: 1e28c9cd9
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.900 . Memory (MB): peak = 1186.641 ; gain = 10.027
Phase 3 Detail Placement
Phase 3.1 Commit Multi Column Macros
Phase 3.1 Commit Multi Column Macros | Checksum: 1e28c9cd9
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.904 . Memory (MB): peak = 1186.641 ; gain = 10.027
Phase 3.2 Commit Most Macros & LUTRAMs
Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 190206097
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.915 . Memory (MB): peak = 1186.641 ; gain = 10.027
Phase 3.3 Area Swap Optimization
Phase 3.3 Area Swap Optimization | Checksum: 1c28d7624
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.921 . Memory (MB): peak = 1186.641 ; gain = 10.027
Phase 3.4 Pipeline Register Optimization
Phase 3.4 Pipeline Register Optimization | Checksum: 1c28d7624
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.923 . Memory (MB): peak = 1186.641 ; gain = 10.027
Phase 3.5 Small Shape Detail Placement
Phase 3.5 Small Shape Detail Placement | Checksum: f59e06de
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.998 . Memory (MB): peak = 1186.641 ; gain = 10.027
Phase 3.6 Re-assign LUT pins
Phase 3.6 Re-assign LUT pins | Checksum: f59e06de
Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1186.641 ; gain = 10.027
Phase 3.7 Pipeline Register Optimization
Phase 3.7 Pipeline Register Optimization | Checksum: f59e06de
Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1186.641 ; gain = 10.027
Phase 3 Detail Placement | Checksum: f59e06de
Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1186.641 ; gain = 10.027
Phase 4 Post Placement Optimization and Clean-Up
Phase 4.1 Post Commit Optimization
Phase 4.1 Post Commit Optimization | Checksum: f59e06de
Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1186.641 ; gain = 10.027
Phase 4.2 Post Placement Cleanup
Phase 4.2 Post Placement Cleanup | Checksum: f59e06de
Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1186.641 ; gain = 10.027
Phase 4.3 Placer Reporting
Phase 4.3 Placer Reporting | Checksum: f59e06de
Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1186.641 ; gain = 10.027
Phase 4.4 Final Placement Cleanup
Phase 4.4 Final Placement Cleanup | Checksum: 1328a0f4c
Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1186.641 ; gain = 10.027
Phase 4 Post Placement Optimization and Clean-Up | Checksum: 1328a0f4c
Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1186.641 ; gain = 10.027
Ending Placer Task | Checksum: 112c44b50
Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1186.641 ; gain = 10.027
INFO: [Common 17-83] Releasing license: Implementation
43 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
place_design completed successfully
INFO: [Timing 38-480] Writing timing data to binary archive.
Writing placer database...
Writing XDEF routing.
Writing XDEF routing logical nets.
Writing XDEF routing special nets.
Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.083 . Memory (MB): peak = 1186.641 ; gain = 0.000
INFO: [Common 17-1381] The checkpoint 'Z:/Storage/Schoolwork/DigitalLogic/test/test.runs/impl_1/t_date_placed.dcp' has been generated.
INFO: [runtcl-4] Executing : report_io -file t_date_io_placed.rpt
report_io: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.033 . Memory (MB): peak = 1189.730 ; gain = 0.000
INFO: [runtcl-4] Executing : report_utilization -file t_date_utilization_placed.rpt -pb t_date_utilization_placed.pb
report_utilization: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.016 . Memory (MB): peak = 1189.730 ; gain = 0.000
INFO: [runtcl-4] Executing : report_control_sets -verbose -file t_date_control_sets_placed.rpt
report_control_sets: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1189.730 ; gain = 0.000
Command: route_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t'
Running DRC as a precondition to command route_design
INFO: [DRC 23-27] Running DRC with 2 threads
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
Starting Routing Task
INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 2 CPUs
Checksum: PlaceDB: 853bba8c ConstDB: 0 ShapeSum: 8d8890c4 RouteDB: 0
Phase 1 Build RT Design
Phase 1 Build RT Design | Checksum: 153020e02
Time (s): cpu = 00:00:07 ; elapsed = 00:00:12 . Memory (MB): peak = 1304.508 ; gain = 114.777
Post Restoration Checksum: NetGraph: 60f072d5 NumContArr: f2119b2d Constraints: 0 Timing: 0
Phase 2 Router Initialization
INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode.
Phase 2.1 Fix Topology Constraints
Phase 2.1 Fix Topology Constraints | Checksum: 153020e02
Time (s): cpu = 00:00:07 ; elapsed = 00:00:12 . Memory (MB): peak = 1310.535 ; gain = 120.805
Phase 2.2 Pre Route Cleanup
Phase 2.2 Pre Route Cleanup | Checksum: 153020e02
Time (s): cpu = 00:00:07 ; elapsed = 00:00:12 . Memory (MB): peak = 1310.535 ; gain = 120.805
Number of Nodes with overlaps = 0
Phase 2 Router Initialization | Checksum: e28d9f17
Time (s): cpu = 00:00:07 ; elapsed = 00:00:12 . Memory (MB): peak = 1315.414 ; gain = 125.684
Phase 3 Initial Routing
Phase 3 Initial Routing | Checksum: c4b27c83
Time (s): cpu = 00:00:07 ; elapsed = 00:00:12 . Memory (MB): peak = 1315.414 ; gain = 125.684
Phase 4 Rip-up And Reroute
Phase 4.1 Global Iteration 0
Number of Nodes with overlaps = 5
Number of Nodes with overlaps = 0
Phase 4.1 Global Iteration 0 | Checksum: 5960c0ac
Time (s): cpu = 00:00:07 ; elapsed = 00:00:12 . Memory (MB): peak = 1315.414 ; gain = 125.684
Phase 4 Rip-up And Reroute | Checksum: 5960c0ac
Time (s): cpu = 00:00:07 ; elapsed = 00:00:12 . Memory (MB): peak = 1315.414 ; gain = 125.684
Phase 5 Delay and Skew Optimization
Phase 5 Delay and Skew Optimization | Checksum: 5960c0ac
Time (s): cpu = 00:00:07 ; elapsed = 00:00:12 . Memory (MB): peak = 1315.414 ; gain = 125.684
Phase 6 Post Hold Fix
Phase 6.1 Hold Fix Iter
Phase 6.1 Hold Fix Iter | Checksum: 5960c0ac
Time (s): cpu = 00:00:07 ; elapsed = 00:00:12 . Memory (MB): peak = 1315.414 ; gain = 125.684
Phase 6 Post Hold Fix | Checksum: 5960c0ac
Time (s): cpu = 00:00:07 ; elapsed = 00:00:12 . Memory (MB): peak = 1315.414 ; gain = 125.684
Phase 7 Route finalize
Router Utilization Summary
Global Vertical Routing Utilization = 0.0249542 %
Global Horizontal Routing Utilization = 0.0217335 %
Routable Net Status*
*Does not include unroutable nets such as driverless and loadless.
Run report_route_status for detailed report.
Number of Failed Nets = 0
Number of Unrouted Nets = 0
Number of Partially Routed Nets = 0
Number of Node Overlaps = 0
Congestion Report
North Dir 1x1 Area, Max Cong = 18.018%, No Congested Regions.
South Dir 1x1 Area, Max Cong = 33.3333%, No Congested Regions.
East Dir 1x1 Area, Max Cong = 19.1176%, No Congested Regions.
West Dir 1x1 Area, Max Cong = 7.35294%, No Congested Regions.
------------------------------
Reporting congestion hotspots
------------------------------
Direction: North
----------------
Congested clusters found at Level 0
Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0
Direction: South
----------------
Congested clusters found at Level 0
Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0
Direction: East
----------------
Congested clusters found at Level 0
Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0
Direction: West
----------------
Congested clusters found at Level 0
Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0
Phase 7 Route finalize | Checksum: 5960c0ac
Time (s): cpu = 00:00:07 ; elapsed = 00:00:12 . Memory (MB): peak = 1315.414 ; gain = 125.684
Phase 8 Verifying routed nets
Verification completed successfully
Phase 8 Verifying routed nets | Checksum: 5960c0ac
Time (s): cpu = 00:00:07 ; elapsed = 00:00:12 . Memory (MB): peak = 1316.297 ; gain = 126.566
Phase 9 Depositing Routes
Phase 9 Depositing Routes | Checksum: 12e8767c6
Time (s): cpu = 00:00:07 ; elapsed = 00:00:12 . Memory (MB): peak = 1316.297 ; gain = 126.566
INFO: [Route 35-16] Router Completed Successfully
Time (s): cpu = 00:00:07 ; elapsed = 00:00:12 . Memory (MB): peak = 1316.297 ; gain = 126.566
Routing Is Done.
INFO: [Common 17-83] Releasing license: Implementation
56 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
route_design completed successfully
route_design: Time (s): cpu = 00:00:08 ; elapsed = 00:00:13 . Memory (MB): peak = 1316.297 ; gain = 126.566
INFO: [Timing 38-480] Writing timing data to binary archive.
Writing placer database...
Writing XDEF routing.
Writing XDEF routing logical nets.
Writing XDEF routing special nets.
Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.081 . Memory (MB): peak = 1316.535 ; gain = 0.238
INFO: [Common 17-1381] The checkpoint 'Z:/Storage/Schoolwork/DigitalLogic/test/test.runs/impl_1/t_date_routed.dcp' has been generated.
INFO: [runtcl-4] Executing : report_drc -file t_date_drc_routed.rpt -pb t_date_drc_routed.pb -rpx t_date_drc_routed.rpx
Command: report_drc -file t_date_drc_routed.rpt -pb t_date_drc_routed.pb -rpx t_date_drc_routed.rpx
INFO: [DRC 23-27] Running DRC with 2 threads
INFO: [Coretcl 2-168] The results of DRC are in file Z:/Storage/Schoolwork/DigitalLogic/test/test.runs/impl_1/t_date_drc_routed.rpt.
report_drc completed successfully
INFO: [runtcl-4] Executing : report_methodology -file t_date_methodology_drc_routed.rpt -pb t_date_methodology_drc_routed.pb -rpx t_date_methodology_drc_routed.rpx
Command: report_methodology -file t_date_methodology_drc_routed.rpt -pb t_date_methodology_drc_routed.pb -rpx t_date_methodology_drc_routed.rpx
INFO: [Timing 38-35] Done setting XDC timing constraints.
INFO: [Timing 38-35] Done setting XDC timing constraints.
INFO: [DRC 23-133] Running Methodology with 2 threads
INFO: [Coretcl 2-1520] The results of Report Methodology are in file Z:/Storage/Schoolwork/DigitalLogic/test/test.runs/impl_1/t_date_methodology_drc_routed.rpt.
report_methodology completed successfully
INFO: [runtcl-4] Executing : report_power -file t_date_power_routed.rpt -pb t_date_power_summary_routed.pb -rpx t_date_power_routed.rpx
Command: report_power -file t_date_power_routed.rpt -pb t_date_power_summary_routed.pb -rpx t_date_power_routed.rpx
WARNING: [Power 33-232] No user defined clocks were found in the design!
Resolution: Please specify clocks using create_clock/create_generated_clock for sequential elements. For pure combinatorial circuits, please specify a virtual clock, otherwise the vectorless estimation might be inaccurate
INFO: [Timing 38-35] Done setting XDC timing constraints.
Running Vector-less Activity Propagation...
Finished Running Vector-less Activity Propagation
68 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered.
report_power completed successfully
INFO: [runtcl-4] Executing : report_route_status -file t_date_route_status.rpt -pb t_date_route_status.pb
INFO: [runtcl-4] Executing : report_timing_summary -max_paths 10 -file t_date_timing_summary_routed.rpt -pb t_date_timing_summary_routed.pb -rpx t_date_timing_summary_routed.rpx -warn_on_violation
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max, Timing Stage: Requireds.
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs
WARNING: [Timing 38-313] There are no user specified timing constraints. Timing constraints are needed for proper timing analysis.
INFO: [runtcl-4] Executing : report_incremental_reuse -file t_date_incremental_reuse_routed.rpt
INFO: [Vivado_Tcl 4-545] No incremental reuse to report, no incremental placement and routing data was found.
INFO: [runtcl-4] Executing : report_clock_utilization -file t_date_clock_utilization_routed.rpt
INFO: [runtcl-4] Executing : report_bus_skew -warn_on_violation -file route_report_bus_skew_0.rpt -rpx route_report_bus_skew_0.rpx
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max, Timing Stage: Requireds.
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs
Command: write_bitstream -force t_date.bit
Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t'
Running DRC as a precondition to command write_bitstream
INFO: [DRC 23-27] Running DRC with 2 threads
WARNING: [DRC CFGBVS-1] Missing CFGBVS and CONFIG_VOLTAGE Design Properties: Neither the CFGBVS nor CONFIG_VOLTAGE voltage property is set in the current_design. Configuration bank voltage select (CFGBVS) must be set to VCCO or GND, and CONFIG_VOLTAGE must be set to the correct configuration voltage, in order to determine the I/O voltage support for the pins in bank 0. It is suggested to specify these either using the 'Edit Device Properties' function in the GUI or directly in the XDC file using the following syntax:
set_property CFGBVS value1 [current_design]
#where value1 is either VCCO or GND
set_property CONFIG_VOLTAGE value2 [current_design]
#where value2 is the voltage provided to configuration bank 0
Refer to the device configuration user guide for more information.
INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings
INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information.
INFO: [Designutils 20-2272] Running write_bitstream with 2 threads.
Loading data files...
Loading site data...
Loading route data...
Processing options...
Creating bitmap...
Creating bitstream...
Writing bitstream ./t_date.bit...
INFO: [Vivado 12-1842] Bitgen Completed Successfully.
INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory.
INFO: [Common 17-83] Releasing license: Implementation
86 Infos, 3 Warnings, 0 Critical Warnings and 0 Errors encountered.
write_bitstream completed successfully
write_bitstream: Time (s): cpu = 00:00:05 ; elapsed = 00:00:08 . Memory (MB): peak = 1750.367 ; gain = 399.805
INFO: [Common 17-206] Exiting Vivado at Thu Dec 19 03:43:44 2024...

160
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@@ -0,0 +1,160 @@
Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
------------------------------------------------------------------------------------
| Tool Version : Vivado v.2018.1 (win64) Build 2188600 Wed Apr 4 18:40:38 MDT 2018
| Date : Thu Dec 19 03:43:36 2024
| Host : WIN-P8FUKGQFPK3 running 64-bit major release (build 9200)
| Command : report_clock_utilization -file t_date_clock_utilization_routed.rpt
| Design : t_date
| Device : 7a35t-csg324
| Speed File : -1 PRODUCTION 1.21 2018-02-08
------------------------------------------------------------------------------------
Clock Utilization Report
Table of Contents
-----------------
1. Clock Primitive Utilization
2. Global Clock Resources
3. Global Clock Source Details
4. Local Clock Details
5. Clock Regions: Key Resource Utilization
6. Clock Regions : Global Clock Summary
7. Device Cell Placement Summary for Global Clock g0
8. Clock Region Cell Placement per Global Clock: Region X1Y1
1. Clock Primitive Utilization
------------------------------
+----------+------+-----------+-----+--------------+--------+
| Type | Used | Available | LOC | Clock Region | Pblock |
+----------+------+-----------+-----+--------------+--------+
| BUFGCTRL | 1 | 32 | 0 | 0 | 0 |
| BUFH | 0 | 72 | 0 | 0 | 0 |
| BUFIO | 0 | 20 | 0 | 0 | 0 |
| BUFMR | 0 | 10 | 0 | 0 | 0 |
| BUFR | 0 | 20 | 0 | 0 | 0 |
| MMCM | 0 | 5 | 0 | 0 | 0 |
| PLL | 0 | 5 | 0 | 0 | 0 |
+----------+------+-----------+-----+--------------+--------+
2. Global Clock Resources
-------------------------
+-----------+-----------+-----------------+------------+---------------+--------------+-------------------+-------------+-----------------+--------------+-------+----------------------+---------------+
| Global Id | Source Id | Driver Type/Pin | Constraint | Site | Clock Region | Load Clock Region | Clock Loads | Non-Clock Loads | Clock Period | Clock | Driver Pin | Net |
+-----------+-----------+-----------------+------------+---------------+--------------+-------------------+-------------+-----------------+--------------+-------+----------------------+---------------+
| g0 | src0 | BUFG/O | None | BUFGCTRL_X0Y0 | n/a | 1 | 40 | 0 | | | clk_IBUF_BUFG_inst/O | clk_IBUF_BUFG |
+-----------+-----------+-----------------+------------+---------------+--------------+-------------------+-------------+-----------------+--------------+-------+----------------------+---------------+
* Clock Loads column represents the clock pin loads (pin count)
** Non-Clock Loads column represents the non-clock pin loads (pin count)
3. Global Clock Source Details
------------------------------
+-----------+-----------+-----------------+------------+-----------+--------------+-------------+-----------------+---------------------+--------------+-----------------+----------+
| Source Id | Global Id | Driver Type/Pin | Constraint | Site | Clock Region | Clock Loads | Non-Clock Loads | Source Clock Period | Source Clock | Driver Pin | Net |
+-----------+-----------+-----------------+------------+-----------+--------------+-------------+-----------------+---------------------+--------------+-----------------+----------+
| src0 | g0 | IBUF/O | IOB_X0Y26 | IOB_X0Y26 | X0Y0 | 1 | 0 | | | clk_IBUF_inst/O | clk_IBUF |
+-----------+-----------+-----------------+------------+-----------+--------------+-------------+-----------------+---------------------+--------------+-----------------+----------+
* Clock Loads column represents the clock pin loads (pin count)
** Non-Clock Loads column represents the non-clock pin loads (pin count)
4. Local Clock Details
----------------------
+----------+-----------------+------------+------------------+--------------+-------------+-----------------+--------------+-------+--------------------+----------------------------------+
| Local Id | Driver Type/Pin | Constraint | Site/BEL | Clock Region | Clock Loads | Non-Clock Loads | Clock Period | Clock | Driver Pin | Net |
+----------+-----------------+------------+------------------+--------------+-------------+-----------------+--------------+-------+--------------------+----------------------------------||
| 0 | FDCE/Q | None | SLICE_X60Y70/AFF | X1Y1 | 22 | 1 | | | U1/clk_20kHZ_reg/Q | U1/CLK - Static -
| 1 | FDCE/Q | None | SLICE_X62Y68/AFF | X1Y1 | 3 | 1 | | | U1/clk_1HZ_reg/Q | U1/FSM_sequential_state_c_reg[2] - Static -
+----------+-----------------+------------+------------------+--------------+-------------+-----------------+--------------+-------+--------------------+----------------------------------||
* Local Clocks in this context represents only clocks driven by non-global buffers
** Clock Loads column represents the clock pin loads (pin count)
*** Non-Clock Loads column represents the non-clock pin loads (pin count)
5. Clock Regions: Key Resource Utilization
------------------------------------------
+-------------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+
| | Global Clock | BUFRs | BUFMRs | BUFIOs | MMCM | PLL | GT | PCI | ILOGIC | OLOGIC | FF | LUTM | RAMB18 | RAMB36 | DSP48E2 |
+-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+
| Clock Region Name | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail |
+-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+
| X0Y0 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 1200 | 0 | 400 | 0 | 20 | 0 | 10 | 0 | 20 |
| X1Y0 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 1500 | 0 | 450 | 0 | 40 | 0 | 20 | 0 | 20 |
| X0Y1 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 1200 | 0 | 400 | 0 | 20 | 0 | 10 | 0 | 20 |
| X1Y1 | 1 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 65 | 1500 | 34 | 450 | 0 | 40 | 0 | 20 | 0 | 20 |
| X0Y2 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 1800 | 0 | 400 | 0 | 20 | 0 | 10 | 0 | 20 |
| X1Y2 | 0 | 12 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 950 | 0 | 300 | 0 | 10 | 0 | 5 | 0 | 20 |
+-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+
* Global Clock column represents track count; while other columns represents cell counts
6. Clock Regions : Global Clock Summary
---------------------------------------
All Modules
+----+----+----+
| | X0 | X1 |
+----+----+----+
| Y2 | 0 | 0 |
| Y1 | 0 | 1 |
| Y0 | 0 | 0 |
+----+----+----+
7. Device Cell Placement Summary for Global Clock g0
----------------------------------------------------
+-----------+-----------------+-------------------+-------+-------------+---------------+-------------+----------+----------------+----------+---------------+
| Global Id | Driver Type/Pin | Driver Region (D) | Clock | Period (ns) | Waveform (ns) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net |
+-----------+-----------------+-------------------+-------+-------------+---------------+-------------+----------+----------------+----------+---------------+
| g0 | BUFG/O | n/a | | | | 40 | 0 | 0 | 0 | clk_IBUF_BUFG |
+-----------+-----------------+-------------------+-------+-------------+---------------+-------------+----------+----------------+----------+---------------+
* Logic Loads column represents load cell count of all cell types other than IO, GT and clock resources
** IO Loads column represents load cell count of IO types
*** Clocking Loads column represents load cell count that are clock resources (global clock buffer, MMCM, PLL, etc)
**** GT Loads column represents load cell count of GT types
+----+----+-----+
| | X0 | X1 |
+----+----+-----+
| Y2 | 0 | 0 |
| Y1 | 0 | 40 |
| Y0 | 0 | 0 |
+----+----+-----+
8. Clock Region Cell Placement per Global Clock: Region X1Y1
------------------------------------------------------------
+-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+-----+----+------+-----+---------+---------------+
| Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | LUTRAM | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net |
+-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+-----+----+------+-----+---------+---------------+
| g0 | n/a | BUFG/O | None | 40 | 0 | 40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | clk_IBUF_BUFG |
+-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+-----+----+------+-----+---------+---------------+
* Clock Loads column represents the clock pin loads (pin count)
** Non-Clock Loads column represents the non-clock pin loads (pin count)
*** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts
# Location of BUFG Primitives
set_property LOC BUFGCTRL_X0Y0 [get_cells clk_IBUF_BUFG_inst]
# Location of IO Primitives which is load of clock spine
# Location of clock ports
set_property LOC IOB_X0Y26 [get_ports clk]
# Clock net "clk_IBUF_BUFG" driven by instance "clk_IBUF_BUFG_inst" located at site "BUFGCTRL_X0Y0"
#startgroup
create_pblock {CLKAG_clk_IBUF_BUFG}
add_cells_to_pblock [get_pblocks {CLKAG_clk_IBUF_BUFG}] [get_cells -filter { PRIMITIVE_GROUP != I/O && IS_PRIMITIVE==1 && PRIMITIVE_LEVEL !=INTERNAL } -of_object [get_pins -filter {DIRECTION==IN} -of_objects [get_nets -hierarchical -filter {PARENT=="clk_IBUF_BUFG"}]]]
resize_pblock [get_pblocks {CLKAG_clk_IBUF_BUFG}] -add {CLOCKREGION_X1Y1:CLOCKREGION_X1Y1}
#endgroup

72
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Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
------------------------------------------------------------------------------------
| Tool Version : Vivado v.2018.1 (win64) Build 2188600 Wed Apr 4 18:40:38 MDT 2018
| Date : Thu Dec 19 03:43:21 2024
| Host : WIN-P8FUKGQFPK3 running 64-bit major release (build 9200)
| Command : report_control_sets -verbose -file t_date_control_sets_placed.rpt
| Design : t_date
| Device : xc7a35t
------------------------------------------------------------------------------------
Control Set Information
Table of Contents
-----------------
1. Summary
2. Histogram
3. Flip-Flop Distribution
4. Detailed Control Set Information
1. Summary
----------
+----------------------------------------------------------+-------+
| Status | Count |
+----------------------------------------------------------+-------+
| Number of unique control sets | 5 |
| Unused register locations in slices containing registers | 7 |
+----------------------------------------------------------+-------+
2. Histogram
------------
+--------+--------------+
| Fanout | Control Sets |
+--------+--------------+
| 3 | 1 |
| 6 | 1 |
| 8 | 2 |
| 16+ | 1 |
+--------+--------------+
3. Flip-Flop Distribution
-------------------------
+--------------+-----------------------+------------------------+-----------------+--------------+
| Clock Enable | Synchronous Set/Reset | Asynchronous Set/Reset | Total Registers | Total Slices |
+--------------+-----------------------+------------------------+-----------------+--------------+
| No | No | No | 0 | 0 |
| No | No | Yes | 43 | 12 |
| No | Yes | No | 8 | 3 |
| Yes | No | No | 14 | 4 |
| Yes | No | Yes | 0 | 0 |
| Yes | Yes | No | 0 | 0 |
+--------------+-----------------------+------------------------+-----------------+--------------+
4. Detailed Control Set Information
-----------------------------------
+-----------------------------------+-----------------+------------------+------------------+----------------+
| Clock Signal | Enable Signal | Set/Reset Signal | Slice Load Count | Bel Load Count |
+-----------------------------------+-----------------+------------------+------------------+----------------+
| U1/FSM_sequential_state_c_reg[2] | | rst_IBUF | 2 | 3 |
| U1/CLK | a_h1[7]_i_1_n_0 | | 1 | 6 |
| U1/CLK | | rst_IBUF | 3 | 8 |
| U1/CLK | a_h2[7]_i_1_n_0 | | 3 | 8 |
| clk_IBUF_BUFG | | rst_IBUF | 10 | 40 |
+-----------------------------------+-----------------+------------------+------------------+----------------+

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Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
---------------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2018.1 (win64) Build 2188600 Wed Apr 4 18:40:38 MDT 2018
| Date : Thu Dec 19 03:43:19 2024
| Host : WIN-P8FUKGQFPK3 running 64-bit major release (build 9200)
| Command : report_drc -file t_date_drc_opted.rpt -pb t_date_drc_opted.pb -rpx t_date_drc_opted.rpx
| Design : t_date
| Device : xc7a35tcsg324-1
| Speed File : -1
| Design State : Synthesized
---------------------------------------------------------------------------------------------------------
Report DRC
Table of Contents
-----------------
1. REPORT SUMMARY
2. REPORT DETAILS
1. REPORT SUMMARY
-----------------
Netlist: netlist
Floorplan: design_1
Design limits: <entire design considered>
Ruledeck: default
Max violations: <unlimited>
Violations found: 1
+----------+----------+-----------------------------------------------------+------------+
| Rule | Severity | Description | Violations |
+----------+----------+-----------------------------------------------------+------------+
| CFGBVS-1 | Warning | Missing CFGBVS and CONFIG_VOLTAGE Design Properties | 1 |
+----------+----------+-----------------------------------------------------+------------+
2. REPORT DETAILS
-----------------
CFGBVS-1#1 Warning
Missing CFGBVS and CONFIG_VOLTAGE Design Properties
Neither the CFGBVS nor CONFIG_VOLTAGE voltage property is set in the current_design. Configuration bank voltage select (CFGBVS) must be set to VCCO or GND, and CONFIG_VOLTAGE must be set to the correct configuration voltage, in order to determine the I/O voltage support for the pins in bank 0. It is suggested to specify these either using the 'Edit Device Properties' function in the GUI or directly in the XDC file using the following syntax:
set_property CFGBVS value1 [current_design]
#where value1 is either VCCO or GND
set_property CONFIG_VOLTAGE value2 [current_design]
#where value2 is the voltage provided to configuration bank 0
Refer to the device configuration user guide for more information.
Related violations: <none>

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Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
------------------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2018.1 (win64) Build 2188600 Wed Apr 4 18:40:38 MDT 2018
| Date : Thu Dec 19 03:43:35 2024
| Host : WIN-P8FUKGQFPK3 running 64-bit major release (build 9200)
| Command : report_drc -file t_date_drc_routed.rpt -pb t_date_drc_routed.pb -rpx t_date_drc_routed.rpx
| Design : t_date
| Device : xc7a35tcsg324-1
| Speed File : -1
| Design State : Routed
------------------------------------------------------------------------------------------------------------
Report DRC
Table of Contents
-----------------
1. REPORT SUMMARY
2. REPORT DETAILS
1. REPORT SUMMARY
-----------------
Netlist: netlist
Floorplan: design_1
Design limits: <entire design considered>
Ruledeck: default
Max violations: <unlimited>
Violations found: 1
+----------+----------+-----------------------------------------------------+------------+
| Rule | Severity | Description | Violations |
+----------+----------+-----------------------------------------------------+------------+
| CFGBVS-1 | Warning | Missing CFGBVS and CONFIG_VOLTAGE Design Properties | 1 |
+----------+----------+-----------------------------------------------------+------------+
2. REPORT DETAILS
-----------------
CFGBVS-1#1 Warning
Missing CFGBVS and CONFIG_VOLTAGE Design Properties
Neither the CFGBVS nor CONFIG_VOLTAGE voltage property is set in the current_design. Configuration bank voltage select (CFGBVS) must be set to VCCO or GND, and CONFIG_VOLTAGE must be set to the correct configuration voltage, in order to determine the I/O voltage support for the pins in bank 0. It is suggested to specify these either using the 'Edit Device Properties' function in the GUI or directly in the XDC file using the following syntax:
set_property CFGBVS value1 [current_design]
#where value1 is either VCCO or GND
set_property CONFIG_VOLTAGE value2 [current_design]
#where value2 is the voltage provided to configuration bank 0
Refer to the device configuration user guide for more information.
Related violations: <none>

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Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
-------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2018.1 (win64) Build 2188600 Wed Apr 4 18:40:38 MDT 2018
| Date : Thu Dec 19 03:43:21 2024
| Host : WIN-P8FUKGQFPK3 running 64-bit major release (build 9200)
| Command : report_io -file t_date_io_placed.rpt
| Design : t_date
| Device : xc7a35t
| Speed File : -1
| Package : csg324
| Package Version : FINAL 2013-12-19
| Package Pin Delay Version : VERS. 2.0 2013-12-19
-------------------------------------------------------------------------------------------------
IO Information
Table of Contents
-----------------
1. Summary
2. IO Assignments by Package Pin
1. Summary
----------
+---------------+
| Total User IO |
+---------------+
| 26 |
+---------------+
2. IO Assignments by Package Pin
--------------------------------
+------------+-------------+------------+------------------------------+-------------+-------------+---------+------------+------+---------------------+----------------------+---------+------------+-----------+----------+------+------------------+--------------+-------------------+--------------+
| Pin Number | Signal Name | Bank Type | Pin Name | Use | IO Standard | IO Bank | Drive (mA) | Slew | On-Chip Termination | Off-Chip Termination | Voltage | Constraint | Pull Type | DQS Bias | Vref | Signal Integrity | Pre Emphasis | Lvds Pre Emphasis | Equalization |
+------------+-------------+------------+------------------------------+-------------+-------------+---------+------------+------+---------------------+----------------------+---------+------------+-----------+----------+------+------------------+--------------+-------------------+--------------+
| A1 | a_h1[3] | High Range | IO_L9N_T1_DQS_AD7N_35 | OUTPUT | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| A2 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| A3 | a_h1[5] | High Range | IO_L8N_T1_AD14N_35 | OUTPUT | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| A4 | a_h1[6] | High Range | IO_L8P_T1_AD14P_35 | OUTPUT | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| A5 | | High Range | IO_L3N_T0_DQS_AD5N_35 | User IO | | 35 | | | | | | | | | | | | | |
| A6 | | High Range | IO_L3P_T0_DQS_AD5P_35 | User IO | | 35 | | | | | | | | | | | | | |
| A7 | | High Range | VCCO_35 | VCCO | | 35 | | | | | 3.30 | | | | | | | | |
| A8 | | High Range | IO_L12N_T1_MRCC_16 | User IO | | 16 | | | | | | | | | | | | | |
| A9 | | High Range | IO_L14N_T2_SRCC_16 | User IO | | 16 | | | | | | | | | | | | | |
| A10 | | High Range | IO_L14P_T2_SRCC_16 | User IO | | 16 | | | | | | | | | | | | | |
| A11 | | High Range | IO_L4N_T0_15 | User IO | | 15 | | | | | | | | | | | | | |
| A12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| A13 | | High Range | IO_L9P_T1_DQS_AD3P_15 | User IO | | 15 | | | | | | | | | | | | | |
| A14 | | High Range | IO_L9N_T1_DQS_AD3N_15 | User IO | | 15 | | | | | | | | | | | | | |
| A15 | | High Range | IO_L8P_T1_AD10P_15 | User IO | | 15 | | | | | | | | | | | | | |
| A16 | | High Range | IO_L8N_T1_AD10N_15 | User IO | | 15 | | | | | | | | | | | | | |
| A17 | | High Range | VCCO_15 | VCCO | | 15 | | | | | any** | | | | | | | | |
| A18 | | High Range | IO_L10N_T1_AD11N_15 | User IO | | 15 | | | | | | | | | | | | | |
| B1 | a_h1[4] | High Range | IO_L9P_T1_DQS_AD7P_35 | OUTPUT | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| B2 | a_h1[1] | High Range | IO_L10N_T1_AD15N_35 | OUTPUT | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| B3 | a_h1[2] | High Range | IO_L10P_T1_AD15P_35 | OUTPUT | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| B4 | a_h1[7] | High Range | IO_L7N_T1_AD6N_35 | OUTPUT | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| B5 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| B6 | | High Range | IO_L2N_T0_AD12N_35 | User IO | | 35 | | | | | | | | | | | | | |
| B7 | | High Range | IO_L2P_T0_AD12P_35 | User IO | | 35 | | | | | | | | | | | | | |
| B8 | | High Range | IO_L12P_T1_MRCC_16 | User IO | | 16 | | | | | | | | | | | | | |
| B9 | | High Range | IO_L11N_T1_SRCC_16 | User IO | | 16 | | | | | | | | | | | | | |
| B10 | | High Range | VCCO_16 | VCCO | | 16 | | | | | any** | | | | | | | | |
| B11 | | High Range | IO_L4P_T0_15 | User IO | | 15 | | | | | | | | | | | | | |
| B12 | | High Range | IO_L3N_T0_DQS_AD1N_15 | User IO | | 15 | | | | | | | | | | | | | |
| B13 | | High Range | IO_L2P_T0_AD8P_15 | User IO | | 15 | | | | | | | | | | | | | |
| B14 | | High Range | IO_L2N_T0_AD8N_15 | User IO | | 15 | | | | | | | | | | | | | |
| B15 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| B16 | | High Range | IO_L7P_T1_AD2P_15 | User IO | | 15 | | | | | | | | | | | | | |
| B17 | | High Range | IO_L7N_T1_AD2N_15 | User IO | | 15 | | | | | | | | | | | | | |
| B18 | | High Range | IO_L10P_T1_AD11P_15 | User IO | | 15 | | | | | | | | | | | | | |
| C1 | an[5] | High Range | IO_L16N_T2_35 | OUTPUT | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| C2 | an[6] | High Range | IO_L16P_T2_35 | OUTPUT | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| C3 | | High Range | VCCO_35 | VCCO | | 35 | | | | | 3.30 | | | | | | | | |
| C4 | | High Range | IO_L7P_T1_AD6P_35 | User IO | | 35 | | | | | | | | | | | | | |
| C5 | | High Range | IO_L1N_T0_AD4N_35 | User IO | | 35 | | | | | | | | | | | | | |
| C6 | | High Range | IO_L1P_T0_AD4P_35 | User IO | | 35 | | | | | | | | | | | | | |
| C7 | | High Range | IO_L4N_T0_35 | User IO | | 35 | | | | | | | | | | | | | |
| C8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| C9 | | High Range | IO_L11P_T1_SRCC_16 | User IO | | 16 | | | | | | | | | | | | | |
| C10 | | High Range | IO_L13N_T2_MRCC_16 | User IO | | 16 | | | | | | | | | | | | | |
| C11 | | High Range | IO_L13P_T2_MRCC_16 | User IO | | 16 | | | | | | | | | | | | | |
| C12 | | High Range | IO_L3P_T0_DQS_AD1P_15 | User IO | | 15 | | | | | | | | | | | | | |
| C13 | | High Range | VCCO_15 | VCCO | | 15 | | | | | any** | | | | | | | | |
| C14 | | High Range | IO_L1N_T0_AD0N_15 | User IO | | 15 | | | | | | | | | | | | | |
| C15 | | High Range | IO_L12N_T1_MRCC_15 | User IO | | 15 | | | | | | | | | | | | | |
| C16 | | High Range | IO_L20P_T3_A20_15 | User IO | | 15 | | | | | | | | | | | | | |
| C17 | | High Range | IO_L20N_T3_A19_15 | User IO | | 15 | | | | | | | | | | | | | |
| C18 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| D1 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| D2 | a_h2[1] | High Range | IO_L14N_T2_SRCC_35 | OUTPUT | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| D3 | a_h2[5] | High Range | IO_L12N_T1_MRCC_35 | OUTPUT | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| D4 | a_h2[7] | High Range | IO_L11N_T1_SRCC_35 | OUTPUT | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| D5 | a_h1[0] | High Range | IO_L11P_T1_SRCC_35 | OUTPUT | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| D6 | | High Range | VCCO_35 | VCCO | | 35 | | | | | 3.30 | | | | | | | | |
| D7 | | High Range | IO_L6N_T0_VREF_35 | User IO | | 35 | | | | | | | | | | | | | |
| D8 | | High Range | IO_L4P_T0_35 | User IO | | 35 | | | | | | | | | | | | | |
| D9 | | High Range | IO_L6N_T0_VREF_16 | User IO | | 16 | | | | | | | | | | | | | |
| D10 | | High Range | IO_L19N_T3_VREF_16 | User IO | | 16 | | | | | | | | | | | | | |
| D11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| D12 | | High Range | IO_L6P_T0_15 | User IO | | 15 | | | | | | | | | | | | | |
| D13 | | High Range | IO_L6N_T0_VREF_15 | User IO | | 15 | | | | | | | | | | | | | |
| D14 | | High Range | IO_L1P_T0_AD0P_15 | User IO | | 15 | | | | | | | | | | | | | |
| D15 | | High Range | IO_L12P_T1_MRCC_15 | User IO | | 15 | | | | | | | | | | | | | |
| D16 | | High Range | VCCO_15 | VCCO | | 15 | | | | | any** | | | | | | | | |
| D17 | | High Range | IO_L16N_T2_A27_15 | User IO | | 15 | | | | | | | | | | | | | |
| D18 | | High Range | IO_L21N_T3_DQS_A18_15 | User IO | | 15 | | | | | | | | | | | | | |
| E1 | an[1] | High Range | IO_L18N_T2_35 | OUTPUT | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| E2 | a_h2[2] | High Range | IO_L14P_T2_SRCC_35 | OUTPUT | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| E3 | a_h2[6] | High Range | IO_L12P_T1_MRCC_35 | OUTPUT | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| E4 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| E5 | | High Range | IO_L5N_T0_AD13N_35 | User IO | | 35 | | | | | | | | | | | | | |
| E6 | | High Range | IO_L5P_T0_AD13P_35 | User IO | | 35 | | | | | | | | | | | | | |
| E7 | | High Range | IO_L6P_T0_35 | User IO | | 35 | | | | | | | | | | | | | |
| E8 | | Dedicated | VCCBATT_0 | Config | | 0 | | | | | | | | | | | | | |
| E9 | | Dedicated | CCLK_0 | Config | | 0 | | | | | | | | | | | | | |
| E10 | | Dedicated | TCK_0 | Config | | 0 | | | | | | | | | | | | | |
| E11 | | Dedicated | TDI_0 | Config | | 0 | | | | | | | | | | | | | |
| E12 | | Dedicated | TMS_0 | Config | | 0 | | | | | | | | | | | | | |
| E13 | | Dedicated | TDO_0 | Config | | 0 | | | | | | | | | | | | | |
| E14 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| E15 | | High Range | IO_L11P_T1_SRCC_15 | User IO | | 15 | | | | | | | | | | | | | |
| E16 | | High Range | IO_L11N_T1_SRCC_15 | User IO | | 15 | | | | | | | | | | | | | |
| E17 | | High Range | IO_L16P_T2_A28_15 | User IO | | 15 | | | | | | | | | | | | | |
| E18 | | High Range | IO_L21P_T3_DQS_15 | User IO | | 15 | | | | | | | | | | | | | |
| F1 | an[2] | High Range | IO_L18P_T2_35 | OUTPUT | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| F2 | | High Range | VCCO_35 | VCCO | | 35 | | | | | 3.30 | | | | | | | | |
| F3 | a_h2[3] | High Range | IO_L13N_T2_MRCC_35 | OUTPUT | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| F4 | a_h2[4] | High Range | IO_L13P_T2_MRCC_35 | OUTPUT | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| F5 | | High Range | IO_0_35 | User IO | | 35 | | | | | | | | | | | | | |
| F6 | | High Range | IO_L19N_T3_VREF_35 | User IO | | 35 | | | | | | | | | | | | | |
| F7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| F8 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
| F9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| F10 | | | VCCBRAM | VCCBRAM | | | | | | | | | | | | | | | |
| F11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| F12 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | |
| F13 | | High Range | IO_L5P_T0_AD9P_15 | User IO | | 15 | | | | | | | | | | | | | |
| F14 | | High Range | IO_L5N_T0_AD9N_15 | User IO | | 15 | | | | | | | | | | | | | |
| F15 | | High Range | IO_L14P_T2_SRCC_15 | User IO | | 15 | | | | | | | | | | | | | |
| F16 | | High Range | IO_L14N_T2_SRCC_15 | User IO | | 15 | | | | | | | | | | | | | |
| F17 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| F18 | | High Range | IO_L22N_T3_A16_15 | User IO | | 15 | | | | | | | | | | | | | |
| G1 | an[3] | High Range | IO_L17N_T2_35 | OUTPUT | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| G2 | an[7] | High Range | IO_L15N_T2_DQS_35 | OUTPUT | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| G3 | | High Range | IO_L20N_T3_35 | User IO | | 35 | | | | | | | | | | | | | |
| G4 | | High Range | IO_L20P_T3_35 | User IO | | 35 | | | | | | | | | | | | | |
| G5 | | High Range | VCCO_35 | VCCO | | 35 | | | | | 3.30 | | | | | | | | |
| G6 | an[0] | High Range | IO_L19P_T3_35 | OUTPUT | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| G7 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
| G8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| G9 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
| G10 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| G11 | | | VCCBRAM | VCCBRAM | | | | | | | | | | | | | | | |
| G12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| G13 | | High Range | IO_0_15 | User IO | | 15 | | | | | | | | | | | | | |
| G14 | | High Range | IO_L15N_T2_DQS_ADV_B_15 | User IO | | 15 | | | | | | | | | | | | | |
| G15 | | High Range | VCCO_15 | VCCO | | 15 | | | | | any** | | | | | | | | |
| G16 | | High Range | IO_L13N_T2_MRCC_15 | User IO | | 15 | | | | | | | | | | | | | |
| G17 | | High Range | IO_L18N_T2_A23_15 | User IO | | 15 | | | | | | | | | | | | | |
| G18 | | High Range | IO_L22P_T3_A17_15 | User IO | | 15 | | | | | | | | | | | | | |
| H1 | an[4] | High Range | IO_L17P_T2_35 | OUTPUT | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| H2 | a_h2[0] | High Range | IO_L15P_T2_DQS_35 | OUTPUT | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| H3 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| H4 | | High Range | IO_L21N_T3_DQS_35 | User IO | | 35 | | | | | | | | | | | | | |
| H5 | | High Range | IO_L24N_T3_35 | User IO | | 35 | | | | | | | | | | | | | |
| H6 | | High Range | IO_L24P_T3_35 | User IO | | 35 | | | | | | | | | | | | | |
| H7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| H8 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
| H9 | | Dedicated | GNDADC_0 | XADC | | 0 | | | | | | | | | | | | | |
| H10 | | Dedicated | VCCADC_0 | XADC | | 0 | | | | | | | | | | | | | |
| H11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| H12 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | |
| H13 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| H14 | | High Range | IO_L15P_T2_DQS_15 | User IO | | 15 | | | | | | | | | | | | | |
| H15 | | High Range | IO_L19N_T3_A21_VREF_15 | User IO | | 15 | | | | | | | | | | | | | |
| H16 | | High Range | IO_L13P_T2_MRCC_15 | User IO | | 15 | | | | | | | | | | | | | |
| H17 | | High Range | IO_L18P_T2_A24_15 | User IO | | 15 | | | | | | | | | | | | | |
| H18 | | High Range | VCCO_15 | VCCO | | 15 | | | | | any** | | | | | | | | |
| J1 | | High Range | VCCO_35 | VCCO | | 35 | | | | | 3.30 | | | | | | | | |
| J2 | | High Range | IO_L22N_T3_35 | User IO | | 35 | | | | | | | | | | | | | |
| J3 | | High Range | IO_L22P_T3_35 | User IO | | 35 | | | | | | | | | | | | | |
| J4 | | High Range | IO_L21P_T3_DQS_35 | User IO | | 35 | | | | | | | | | | | | | |
| J5 | | High Range | IO_25_35 | User IO | | 35 | | | | | | | | | | | | | |
| J6 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| J7 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
| J8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| J9 | | Dedicated | VREFN_0 | XADC | | 0 | | | | | | | | | | | | | |
| J10 | | Dedicated | VP_0 | XADC | | 0 | | | | | | | | | | | | | |
| J11 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
| J12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| J13 | | High Range | IO_L17N_T2_A25_15 | User IO | | 15 | | | | | | | | | | | | | |
| J14 | | High Range | IO_L19P_T3_A22_15 | User IO | | 15 | | | | | | | | | | | | | |
| J15 | | High Range | IO_L24N_T3_RS0_15 | User IO | | 15 | | | | | | | | | | | | | |
| J16 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| J17 | | High Range | IO_L23P_T3_FOE_B_15 | User IO | | 15 | | | | | | | | | | | | | |
| J18 | | High Range | IO_L23N_T3_FWE_B_15 | User IO | | 15 | | | | | | | | | | | | | |
| K1 | | High Range | IO_L23N_T3_35 | User IO | | 35 | | | | | | | | | | | | | |
| K2 | | High Range | IO_L23P_T3_35 | User IO | | 35 | | | | | | | | | | | | | |
| K3 | | High Range | IO_L2P_T0_34 | User IO | | 34 | | | | | | | | | | | | | |
| K4 | | High Range | VCCO_34 | VCCO | | 34 | | | | | any** | | | | | | | | |
| K5 | | High Range | IO_L5P_T0_34 | User IO | | 34 | | | | | | | | | | | | | |
| K6 | | High Range | IO_0_34 | User IO | | 34 | | | | | | | | | | | | | |
| K7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| K8 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
| K9 | | Dedicated | VN_0 | XADC | | 0 | | | | | | | | | | | | | |
| K10 | | Dedicated | VREFP_0 | XADC | | 0 | | | | | | | | | | | | | |
| K11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| K12 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | |
| K13 | | High Range | IO_L17P_T2_A26_15 | User IO | | 15 | | | | | | | | | | | | | |
| K14 | | High Range | VCCO_15 | VCCO | | 15 | | | | | any** | | | | | | | | |
| K15 | | High Range | IO_L24P_T3_RS1_15 | User IO | | 15 | | | | | | | | | | | | | |
| K16 | | High Range | IO_25_15 | User IO | | 15 | | | | | | | | | | | | | |
| K17 | | High Range | IO_L1P_T0_D00_MOSI_14 | User IO | | 14 | | | | | | | | | | | | | |
| K18 | | High Range | IO_L1N_T0_D01_DIN_14 | User IO | | 14 | | | | | | | | | | | | | |
| L1 | | High Range | IO_L1P_T0_34 | User IO | | 34 | | | | | | | | | | | | | |
| L2 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| L3 | | High Range | IO_L2N_T0_34 | User IO | | 34 | | | | | | | | | | | | | |
| L4 | | High Range | IO_L5N_T0_34 | User IO | | 34 | | | | | | | | | | | | | |
| L5 | | High Range | IO_L6N_T0_VREF_34 | User IO | | 34 | | | | | | | | | | | | | |
| L6 | | High Range | IO_L6P_T0_34 | User IO | | 34 | | | | | | | | | | | | | |
| L7 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
| L8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| L9 | | Dedicated | DXN_0 | Temp Sensor | | 0 | | | | | | | | | | | | | |
| L10 | | Dedicated | DXP_0 | Temp Sensor | | 0 | | | | | | | | | | | | | |
| L11 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
| L12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| L13 | | High Range | IO_L6P_T0_FCS_B_14 | User IO | | 14 | | | | | | | | | | | | | |
| L14 | | High Range | IO_L2P_T0_D02_14 | User IO | | 14 | | | | | | | | | | | | | |
| L15 | | High Range | IO_L3P_T0_DQS_PUDC_B_14 | User IO | | 14 | | | | | | | | | | | | | |
| L16 | | High Range | IO_L3N_T0_DQS_EMCCLK_14 | User IO | | 14 | | | | | | | | | | | | | |
| L17 | | High Range | VCCO_14 | VCCO | | 14 | | | | | 3.30 | | | | | | | | |
| L18 | | High Range | IO_L4P_T0_D04_14 | User IO | | 14 | | | | | | | | | | | | | |
| M1 | | High Range | IO_L1N_T0_34 | User IO | | 34 | | | | | | | | | | | | | |
| M2 | | High Range | IO_L4N_T0_34 | User IO | | 34 | | | | | | | | | | | | | |
| M3 | | High Range | IO_L4P_T0_34 | User IO | | 34 | | | | | | | | | | | | | |
| M4 | | High Range | IO_L16P_T2_34 | User IO | | 34 | | | | | | | | | | | | | |
| M5 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| M6 | | High Range | IO_L18P_T2_34 | User IO | | 34 | | | | | | | | | | | | | |
| M7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| M8 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
| M9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| M10 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
| M11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| M12 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | |
| M13 | | High Range | IO_L6N_T0_D08_VREF_14 | User IO | | 14 | | | | | | | | | | | | | |
| M14 | | High Range | IO_L2N_T0_D03_14 | User IO | | 14 | | | | | | | | | | | | | |
| M15 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| M16 | | High Range | IO_L10P_T1_D14_14 | User IO | | 14 | | | | | | | | | | | | | |
| M17 | | High Range | IO_L10N_T1_D15_14 | User IO | | 14 | | | | | | | | | | | | | |
| M18 | | High Range | IO_L4N_T0_D05_14 | User IO | | 14 | | | | | | | | | | | | | |
| N1 | | High Range | IO_L3N_T0_DQS_34 | User IO | | 34 | | | | | | | | | | | | | |
| N2 | | High Range | IO_L3P_T0_DQS_34 | User IO | | 34 | | | | | | | | | | | | | |
| N3 | | High Range | VCCO_34 | VCCO | | 34 | | | | | any** | | | | | | | | |
| N4 | | High Range | IO_L16N_T2_34 | User IO | | 34 | | | | | | | | | | | | | |
| N5 | | High Range | IO_L13P_T2_MRCC_34 | User IO | | 34 | | | | | | | | | | | | | |
| N6 | | High Range | IO_L18N_T2_34 | User IO | | 34 | | | | | | | | | | | | | |
| N7 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
| N8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| N9 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
| N10 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| N11 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
| N12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| N13 | | High Range | VCCO_14 | VCCO | | 14 | | | | | 3.30 | | | | | | | | |
| N14 | | High Range | IO_L8P_T1_D11_14 | User IO | | 14 | | | | | | | | | | | | | |
| N15 | | High Range | IO_L11P_T1_SRCC_14 | User IO | | 14 | | | | | | | | | | | | | |
| N16 | | High Range | IO_L11N_T1_SRCC_14 | User IO | | 14 | | | | | | | | | | | | | |
| N17 | | High Range | IO_L9P_T1_DQS_14 | User IO | | 14 | | | | | | | | | | | | | |
| N18 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| P1 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| P2 | | High Range | IO_L15P_T2_DQS_34 | User IO | | 34 | | | | | | | | | | | | | |
| P3 | | High Range | IO_L14N_T2_SRCC_34 | User IO | | 34 | | | | | | | | | | | | | |
| P4 | | High Range | IO_L14P_T2_SRCC_34 | User IO | | 34 | | | | | | | | | | | | | |
| P5 | | High Range | IO_L13N_T2_MRCC_34 | User IO | | 34 | | | | | | | | | | | | | |
| P6 | | High Range | VCCO_34 | VCCO | | 34 | | | | | any** | | | | | | | | |
| P7 | | Dedicated | INIT_B_0 | Config | | 0 | | | | | | | | | | | | | |
| P8 | | Dedicated | CFGBVS_0 | Config | | 0 | | | | | | | | | | | | | |
| P9 | | Dedicated | PROGRAM_B_0 | Config | | 0 | | | | | | | | | | | | | |
| P10 | | Dedicated | DONE_0 | Config | | 0 | | | | | | | | | | | | | |
| P11 | | Dedicated | M2_0 | Config | | 0 | | | | | | | | | | | | | |
| P12 | | Dedicated | M0_0 | Config | | 0 | | | | | | | | | | | | | |
| P13 | | Dedicated | M1_0 | Config | | 0 | | | | | | | | | | | | | |
| P14 | | High Range | IO_L8N_T1_D12_14 | User IO | | 14 | | | | | | | | | | | | | |
| P15 | | High Range | IO_L13P_T2_MRCC_14 | User IO | | 14 | | | | | | | | | | | | | |
| P16 | | High Range | VCCO_14 | VCCO | | 14 | | | | | 3.30 | | | | | | | | |
| P17 | clk | High Range | IO_L12P_T1_MRCC_14 | INPUT | LVCMOS33 | 14 | | | | NONE | | FIXED | | | | NONE | | | |
| P18 | | High Range | IO_L9N_T1_DQS_D13_14 | User IO | | 14 | | | | | | | | | | | | | |
| R1 | | High Range | IO_L17P_T2_34 | User IO | | 34 | | | | | | | | | | | | | |
| R2 | | High Range | IO_L15N_T2_DQS_34 | User IO | | 34 | | | | | | | | | | | | | |
| R3 | | High Range | IO_L11P_T1_SRCC_34 | User IO | | 34 | | | | | | | | | | | | | |
| R4 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| R5 | | High Range | IO_L19N_T3_VREF_34 | User IO | | 34 | | | | | | | | | | | | | |
| R6 | | High Range | IO_L19P_T3_34 | User IO | | 34 | | | | | | | | | | | | | |
| R7 | | High Range | IO_L23P_T3_34 | User IO | | 34 | | | | | | | | | | | | | |
| R8 | | High Range | IO_L24P_T3_34 | User IO | | 34 | | | | | | | | | | | | | |
| R9 | | Dedicated | VCCO_0 | VCCO | | 0 | | | | | any** | | | | | | | | |
| R10 | | High Range | IO_25_14 | User IO | | 14 | | | | | | | | | | | | | |
| R11 | | High Range | IO_0_14 | User IO | | 14 | | | | | | | | | | | | | |
| R12 | | High Range | IO_L5P_T0_D06_14 | User IO | | 14 | | | | | | | | | | | | | |
| R13 | | High Range | IO_L5N_T0_D07_14 | User IO | | 14 | | | | | | | | | | | | | |
| R14 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| R15 | rst | High Range | IO_L13N_T2_MRCC_14 | INPUT | LVCMOS33 | 14 | | | | NONE | | FIXED | | | | NONE | | | |
| R16 | | High Range | IO_L15P_T2_DQS_RDWR_B_14 | User IO | | 14 | | | | | | | | | | | | | |
| R17 | | High Range | IO_L12N_T1_MRCC_14 | User IO | | 14 | | | | | | | | | | | | | |
| R18 | | High Range | IO_L7P_T1_D09_14 | User IO | | 14 | | | | | | | | | | | | | |
| T1 | | High Range | IO_L17N_T2_34 | User IO | | 34 | | | | | | | | | | | | | |
| T2 | | High Range | VCCO_34 | VCCO | | 34 | | | | | any** | | | | | | | | |
| T3 | | High Range | IO_L11N_T1_SRCC_34 | User IO | | 34 | | | | | | | | | | | | | |
| T4 | | High Range | IO_L12N_T1_MRCC_34 | User IO | | 34 | | | | | | | | | | | | | |
| T5 | | High Range | IO_L12P_T1_MRCC_34 | User IO | | 34 | | | | | | | | | | | | | |
| T6 | | High Range | IO_L23N_T3_34 | User IO | | 34 | | | | | | | | | | | | | |
| T7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| T8 | | High Range | IO_L24N_T3_34 | User IO | | 34 | | | | | | | | | | | | | |
| T9 | | High Range | IO_L24P_T3_A01_D17_14 | User IO | | 14 | | | | | | | | | | | | | |
| T10 | | High Range | IO_L24N_T3_A00_D16_14 | User IO | | 14 | | | | | | | | | | | | | |
| T11 | | High Range | IO_L19P_T3_A10_D26_14 | User IO | | 14 | | | | | | | | | | | | | |
| T12 | | High Range | VCCO_14 | VCCO | | 14 | | | | | 3.30 | | | | | | | | |
| T13 | | High Range | IO_L23P_T3_A03_D19_14 | User IO | | 14 | | | | | | | | | | | | | |
| T14 | | High Range | IO_L14P_T2_SRCC_14 | User IO | | 14 | | | | | | | | | | | | | |
| T15 | | High Range | IO_L14N_T2_SRCC_14 | User IO | | 14 | | | | | | | | | | | | | |
| T16 | | High Range | IO_L15N_T2_DQS_DOUT_CSO_B_14 | User IO | | 14 | | | | | | | | | | | | | |
| T17 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| T18 | | High Range | IO_L7N_T1_D10_14 | User IO | | 14 | | | | | | | | | | | | | |
| U1 | | High Range | IO_L7P_T1_34 | User IO | | 34 | | | | | | | | | | | | | |
| U2 | | High Range | IO_L9P_T1_DQS_34 | User IO | | 34 | | | | | | | | | | | | | |
| U3 | | High Range | IO_L8N_T1_34 | User IO | | 34 | | | | | | | | | | | | | |
| U4 | | High Range | IO_L8P_T1_34 | User IO | | 34 | | | | | | | | | | | | | |
| U5 | | High Range | VCCO_34 | VCCO | | 34 | | | | | any** | | | | | | | | |
| U6 | | High Range | IO_L22N_T3_34 | User IO | | 34 | | | | | | | | | | | | | |
| U7 | | High Range | IO_L22P_T3_34 | User IO | | 34 | | | | | | | | | | | | | |
| U8 | | High Range | IO_25_34 | User IO | | 34 | | | | | | | | | | | | | |
| U9 | | High Range | IO_L21P_T3_DQS_34 | User IO | | 34 | | | | | | | | | | | | | |
| U10 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| U11 | | High Range | IO_L19N_T3_A09_D25_VREF_14 | User IO | | 14 | | | | | | | | | | | | | |
| U12 | | High Range | IO_L20P_T3_A08_D24_14 | User IO | | 14 | | | | | | | | | | | | | |
| U13 | | High Range | IO_L23N_T3_A02_D18_14 | User IO | | 14 | | | | | | | | | | | | | |
| U14 | | High Range | IO_L22P_T3_A05_D21_14 | User IO | | 14 | | | | | | | | | | | | | |
| U15 | | High Range | VCCO_14 | VCCO | | 14 | | | | | 3.30 | | | | | | | | |
| U16 | | High Range | IO_L18P_T2_A12_D28_14 | User IO | | 14 | | | | | | | | | | | | | |
| U17 | | High Range | IO_L17P_T2_A14_D30_14 | User IO | | 14 | | | | | | | | | | | | | |
| U18 | | High Range | IO_L17N_T2_A13_D29_14 | User IO | | 14 | | | | | | | | | | | | | |
| V1 | | High Range | IO_L7N_T1_34 | User IO | | 34 | | | | | | | | | | | | | |
| V2 | | High Range | IO_L9N_T1_DQS_34 | User IO | | 34 | | | | | | | | | | | | | |
| V3 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| V4 | | High Range | IO_L10N_T1_34 | User IO | | 34 | | | | | | | | | | | | | |
| V5 | | High Range | IO_L10P_T1_34 | User IO | | 34 | | | | | | | | | | | | | |
| V6 | | High Range | IO_L20N_T3_34 | User IO | | 34 | | | | | | | | | | | | | |
| V7 | | High Range | IO_L20P_T3_34 | User IO | | 34 | | | | | | | | | | | | | |
| V8 | | High Range | VCCO_34 | VCCO | | 34 | | | | | any** | | | | | | | | |
| V9 | | High Range | IO_L21N_T3_DQS_34 | User IO | | 34 | | | | | | | | | | | | | |
| V10 | | High Range | IO_L21P_T3_DQS_14 | User IO | | 14 | | | | | | | | | | | | | |
| V11 | | High Range | IO_L21N_T3_DQS_A06_D22_14 | User IO | | 14 | | | | | | | | | | | | | |
| V12 | | High Range | IO_L20N_T3_A07_D23_14 | User IO | | 14 | | | | | | | | | | | | | |
| V13 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| V14 | | High Range | IO_L22N_T3_A04_D20_14 | User IO | | 14 | | | | | | | | | | | | | |
| V15 | | High Range | IO_L16P_T2_CSI_B_14 | User IO | | 14 | | | | | | | | | | | | | |
| V16 | | High Range | IO_L16N_T2_A15_D31_14 | User IO | | 14 | | | | | | | | | | | | | |
| V17 | | High Range | IO_L18N_T2_A11_D27_14 | User IO | | 14 | | | | | | | | | | | | | |
| V18 | | High Range | VCCO_14 | VCCO | | 14 | | | | | 3.30 | | | | | | | | |
+------------+-------------+------------+------------------------------+-------------+-------------+---------+------------+------+---------------------+----------------------+---------+------------+-----------+----------+------+------------------+--------------+-------------------+--------------+
* Default value
** Special VCCO requirements may apply. Please consult the device family datasheet for specific guideline on VCCO requirements.

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Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
--------------------------------------------------------------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2018.1 (win64) Build 2188600 Wed Apr 4 18:40:38 MDT 2018
| Date : Thu Dec 19 03:43:35 2024
| Host : WIN-P8FUKGQFPK3 running 64-bit major release (build 9200)
| Command : report_methodology -file t_date_methodology_drc_routed.rpt -pb t_date_methodology_drc_routed.pb -rpx t_date_methodology_drc_routed.rpx
| Design : t_date
| Device : xc7a35tcsg324-1
| Speed File : -1
| Design State : Routed
--------------------------------------------------------------------------------------------------------------------------------------------------------
Report Methodology
Table of Contents
-----------------
1. REPORT SUMMARY
2. REPORT DETAILS
1. REPORT SUMMARY
-----------------
Netlist: netlist
Floorplan: design_1
Design limits: <entire design considered>
Max violations: <unlimited>
Violations found: 65
+-----------+----------+-----------------------------+------------+
| Rule | Severity | Description | Violations |
+-----------+----------+-----------------------------+------------+
| TIMING-17 | Warning | Non-clocked sequential cell | 65 |
+-----------+----------+-----------------------------+------------+
2. REPORT DETAILS
-----------------
TIMING-17#1 Warning
Non-clocked sequential cell
The clock pin FSM_sequential_state_c_reg[0]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#2 Warning
Non-clocked sequential cell
The clock pin FSM_sequential_state_c_reg[1]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#3 Warning
Non-clocked sequential cell
The clock pin FSM_sequential_state_c_reg[2]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#4 Warning
Non-clocked sequential cell
The clock pin U1/clk_1HZ_reg/C is not reached by a timing clock
Related violations: <none>
TIMING-17#5 Warning
Non-clocked sequential cell
The clock pin U1/clk_20kHZ_reg/C is not reached by a timing clock
Related violations: <none>
TIMING-17#6 Warning
Non-clocked sequential cell
The clock pin U1/counter1_reg[0]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#7 Warning
Non-clocked sequential cell
The clock pin U1/counter1_reg[10]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#8 Warning
Non-clocked sequential cell
The clock pin U1/counter1_reg[11]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#9 Warning
Non-clocked sequential cell
The clock pin U1/counter1_reg[12]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#10 Warning
Non-clocked sequential cell
The clock pin U1/counter1_reg[13]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#11 Warning
Non-clocked sequential cell
The clock pin U1/counter1_reg[14]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#12 Warning
Non-clocked sequential cell
The clock pin U1/counter1_reg[15]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#13 Warning
Non-clocked sequential cell
The clock pin U1/counter1_reg[16]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#14 Warning
Non-clocked sequential cell
The clock pin U1/counter1_reg[17]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#15 Warning
Non-clocked sequential cell
The clock pin U1/counter1_reg[18]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#16 Warning
Non-clocked sequential cell
The clock pin U1/counter1_reg[19]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#17 Warning
Non-clocked sequential cell
The clock pin U1/counter1_reg[1]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#18 Warning
Non-clocked sequential cell
The clock pin U1/counter1_reg[20]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#19 Warning
Non-clocked sequential cell
The clock pin U1/counter1_reg[21]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#20 Warning
Non-clocked sequential cell
The clock pin U1/counter1_reg[22]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#21 Warning
Non-clocked sequential cell
The clock pin U1/counter1_reg[23]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#22 Warning
Non-clocked sequential cell
The clock pin U1/counter1_reg[24]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#23 Warning
Non-clocked sequential cell
The clock pin U1/counter1_reg[25]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#24 Warning
Non-clocked sequential cell
The clock pin U1/counter1_reg[2]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#25 Warning
Non-clocked sequential cell
The clock pin U1/counter1_reg[3]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#26 Warning
Non-clocked sequential cell
The clock pin U1/counter1_reg[4]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#27 Warning
Non-clocked sequential cell
The clock pin U1/counter1_reg[5]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#28 Warning
Non-clocked sequential cell
The clock pin U1/counter1_reg[6]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#29 Warning
Non-clocked sequential cell
The clock pin U1/counter1_reg[7]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#30 Warning
Non-clocked sequential cell
The clock pin U1/counter1_reg[8]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#31 Warning
Non-clocked sequential cell
The clock pin U1/counter1_reg[9]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#32 Warning
Non-clocked sequential cell
The clock pin U1/counter20k_reg[0]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#33 Warning
Non-clocked sequential cell
The clock pin U1/counter20k_reg[10]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#34 Warning
Non-clocked sequential cell
The clock pin U1/counter20k_reg[11]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#35 Warning
Non-clocked sequential cell
The clock pin U1/counter20k_reg[1]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#36 Warning
Non-clocked sequential cell
The clock pin U1/counter20k_reg[2]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#37 Warning
Non-clocked sequential cell
The clock pin U1/counter20k_reg[3]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#38 Warning
Non-clocked sequential cell
The clock pin U1/counter20k_reg[4]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#39 Warning
Non-clocked sequential cell
The clock pin U1/counter20k_reg[5]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#40 Warning
Non-clocked sequential cell
The clock pin U1/counter20k_reg[6]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#41 Warning
Non-clocked sequential cell
The clock pin U1/counter20k_reg[7]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#42 Warning
Non-clocked sequential cell
The clock pin U1/counter20k_reg[8]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#43 Warning
Non-clocked sequential cell
The clock pin U1/counter20k_reg[9]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#44 Warning
Non-clocked sequential cell
The clock pin a_h1_reg[1]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#45 Warning
Non-clocked sequential cell
The clock pin a_h1_reg[2]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#46 Warning
Non-clocked sequential cell
The clock pin a_h1_reg[5]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#47 Warning
Non-clocked sequential cell
The clock pin a_h1_reg[7]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#48 Warning
Non-clocked sequential cell
The clock pin a_h1_reg[7]_lopt_replica/C is not reached by a timing clock
Related violations: <none>
TIMING-17#49 Warning
Non-clocked sequential cell
The clock pin a_h1_reg[7]_lopt_replica_2/C is not reached by a timing clock
Related violations: <none>
TIMING-17#50 Warning
Non-clocked sequential cell
The clock pin a_h2_reg[0]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#51 Warning
Non-clocked sequential cell
The clock pin a_h2_reg[1]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#52 Warning
Non-clocked sequential cell
The clock pin a_h2_reg[2]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#53 Warning
Non-clocked sequential cell
The clock pin a_h2_reg[5]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#54 Warning
Non-clocked sequential cell
The clock pin a_h2_reg[6]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#55 Warning
Non-clocked sequential cell
The clock pin a_h2_reg[7]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#56 Warning
Non-clocked sequential cell
The clock pin a_h2_reg[7]_lopt_replica/C is not reached by a timing clock
Related violations: <none>
TIMING-17#57 Warning
Non-clocked sequential cell
The clock pin a_h2_reg[7]_lopt_replica_2/C is not reached by a timing clock
Related violations: <none>
TIMING-17#58 Warning
Non-clocked sequential cell
The clock pin an_reg[0]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#59 Warning
Non-clocked sequential cell
The clock pin an_reg[1]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#60 Warning
Non-clocked sequential cell
The clock pin an_reg[2]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#61 Warning
Non-clocked sequential cell
The clock pin an_reg[3]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#62 Warning
Non-clocked sequential cell
The clock pin an_reg[4]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#63 Warning
Non-clocked sequential cell
The clock pin an_reg[5]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#64 Warning
Non-clocked sequential cell
The clock pin an_reg[6]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#65 Warning
Non-clocked sequential cell
The clock pin an_reg[7]/C is not reached by a timing clock
Related violations: <none>

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Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
----------------------------------------------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2018.1 (win64) Build 2188600 Wed Apr 4 18:40:38 MDT 2018
| Date : Thu Dec 19 03:43:36 2024
| Host : WIN-P8FUKGQFPK3 running 64-bit major release (build 9200)
| Command : report_power -file t_date_power_routed.rpt -pb t_date_power_summary_routed.pb -rpx t_date_power_routed.rpx
| Design : t_date
| Device : xc7a35tcsg324-1
| Design State : routed
| Grade : commercial
| Process : typical
| Characterization : Production
----------------------------------------------------------------------------------------------------------------------------------------
Power Report
Table of Contents
-----------------
1. Summary
1.1 On-Chip Components
1.2 Power Supply Summary
1.3 Confidence Level
2. Settings
2.1 Environment
2.2 Clock Constraints
3. Detailed Reports
3.1 By Hierarchy
1. Summary
----------
+--------------------------+--------------+
| Total On-Chip Power (W) | 10.151 |
| Design Power Budget (W) | Unspecified* |
| Power Budget Margin (W) | NA |
| Dynamic (W) | 10.016 |
| Device Static (W) | 0.136 |
| Effective TJA (C/W) | 4.8 |
| Max Ambient (C) | 36.5 |
| Junction Temperature (C) | 73.5 |
| Confidence Level | Low |
| Setting File | --- |
| Simulation Activity File | --- |
| Design Nets Matched | NA |
+--------------------------+--------------+
* Specify Design Power Budget using, set_operating_conditions -design_power_budget <value in Watts>
1.1 On-Chip Components
----------------------
+----------------+-----------+----------+-----------+-----------------+
| On-Chip | Power (W) | Used | Available | Utilization (%) |
+----------------+-----------+----------+-----------+-----------------+
| Slice Logic | 0.617 | 163 | --- | --- |
| LUT as Logic | 0.552 | 63 | 20800 | 0.30 |
| Register | 0.030 | 65 | 41600 | 0.16 |
| CARRY4 | 0.029 | 10 | 8150 | 0.12 |
| BUFG | 0.006 | 1 | 32 | 3.13 |
| Others | 0.000 | 4 | --- | --- |
| Signals | 0.505 | 137 | --- | --- |
| I/O | 8.894 | 26 | 210 | 12.38 |
| Static Power | 0.136 | | | |
| Total | 10.151 | | | |
+----------------+-----------+----------+-----------+-----------------+
1.2 Power Supply Summary
------------------------
+-----------+-------------+-----------+-------------+------------+
| Source | Voltage (V) | Total (A) | Dynamic (A) | Static (A) |
+-----------+-------------+-----------+-------------+------------+
| Vccint | 1.000 | 1.188 | 1.126 | 0.062 |
| Vccaux | 1.800 | 0.344 | 0.326 | 0.018 |
| Vcco33 | 3.300 | 2.517 | 2.516 | 0.001 |
| Vcco25 | 2.500 | 0.000 | 0.000 | 0.000 |
| Vcco18 | 1.800 | 0.000 | 0.000 | 0.000 |
| Vcco15 | 1.500 | 0.000 | 0.000 | 0.000 |
| Vcco135 | 1.350 | 0.000 | 0.000 | 0.000 |
| Vcco12 | 1.200 | 0.000 | 0.000 | 0.000 |
| Vccaux_io | 1.800 | 0.000 | 0.000 | 0.000 |
| Vccbram | 1.000 | 0.001 | 0.000 | 0.001 |
| MGTAVcc | 1.000 | 0.000 | 0.000 | 0.000 |
| MGTAVtt | 1.200 | 0.000 | 0.000 | 0.000 |
| Vccadc | 1.800 | 0.020 | 0.000 | 0.020 |
+-----------+-------------+-----------+-------------+------------+
1.3 Confidence Level
--------------------
+-----------------------------+------------+--------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------+
| User Input Data | Confidence | Details | Action |
+-----------------------------+------------+--------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------+
| Design implementation state | High | Design is routed | |
| Clock nodes activity | Low | User specified less than 75% of clocks | Provide missing clock activity with a constraint file, simulation results or by editing the "By Clock Domain" view |
| I/O nodes activity | Low | More than 75% of inputs are missing user specification | Provide missing input activity with simulation results or by editing the "By Resource Type -> I/Os" view |
| Internal nodes activity | Medium | User specified less than 25% of internal nodes | Provide missing internal nodes activity with simulation results or by editing the "By Resource Type" views |
| Device models | High | Device models are Production | |
| | | | |
| Overall confidence level | Low | | |
+-----------------------------+------------+--------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------+
2. Settings
-----------
2.1 Environment
---------------
+-----------------------+--------------------------+
| Ambient Temp (C) | 25.0 |
| ThetaJA (C/W) | 4.8 |
| Airflow (LFM) | 250 |
| Heat Sink | medium (Medium Profile) |
| ThetaSA (C/W) | 4.6 |
| Board Selection | medium (10"x10") |
| # of Board Layers | 12to15 (12 to 15 Layers) |
| Board Temperature (C) | 25.0 |
+-----------------------+--------------------------+
2.2 Clock Constraints
---------------------
+-------+--------+-----------------+
| Clock | Domain | Constraint (ns) |
+-------+--------+-----------------+
3. Detailed Reports
-------------------
3.1 By Hierarchy
----------------
+--------+-----------+
| Name | Power (W) |
+--------+-----------+
| t_date | 10.016 |
| U1 | 0.473 |
+--------+-----------+

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Design Route Status
: # nets :
------------------------------------------- : ----------- :
# of logical nets.......................... : 223 :
# of nets not needing routing.......... : 84 :
# of internally routed nets........ : 84 :
# of routable nets..................... : 139 :
# of fully routed nets............. : 139 :
# of nets with routing errors.......... : 0 :
------------------------------------------- : ----------- :

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2012.4’)Timing analysis from Implemented netlist.

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Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2018.1 (win64) Build 2188600 Wed Apr 4 18:40:38 MDT 2018
| Date : Thu Dec 19 03:43:36 2024
| Host : WIN-P8FUKGQFPK3 running 64-bit major release (build 9200)
| Command : report_timing_summary -max_paths 10 -file t_date_timing_summary_routed.rpt -pb t_date_timing_summary_routed.pb -rpx t_date_timing_summary_routed.rpx -warn_on_violation
| Design : t_date
| Device : 7a35t-csg324
| Speed File : -1 PRODUCTION 1.21 2018-02-08
-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
Timing Summary Report
------------------------------------------------------------------------------------------------
| Timer Settings
| --------------
------------------------------------------------------------------------------------------------
Enable Multi Corner Analysis : Yes
Enable Pessimism Removal : Yes
Pessimism Removal Resolution : Nearest Common Node
Enable Input Delay Default Clock : No
Enable Preset / Clear Arcs : No
Disable Flight Delays : No
Ignore I/O Paths : No
Timing Early Launch at Borrowing Latches : false
Corner Analyze Analyze
Name Max Paths Min Paths
------ --------- ---------
Slow Yes Yes
Fast Yes Yes
check_timing report
Table of Contents
-----------------
1. checking no_clock
2. checking constant_clock
3. checking pulse_width_clock
4. checking unconstrained_internal_endpoints
5. checking no_input_delay
6. checking no_output_delay
7. checking multiple_clock
8. checking generated_clocks
9. checking loops
10. checking partial_input_delay
11. checking partial_output_delay
12. checking latch_loops
1. checking no_clock
--------------------
There are 40 register/latch pins with no clock driven by root clock pin: clk (HIGH)
There are 3 register/latch pins with no clock driven by root clock pin: U1/clk_1HZ_reg/Q (HIGH)
There are 22 register/latch pins with no clock driven by root clock pin: U1/clk_20kHZ_reg/Q (HIGH)
2. checking constant_clock
--------------------------
There are 0 register/latch pins with constant_clock.
3. checking pulse_width_clock
-----------------------------
There are 0 register/latch pins which need pulse_width check
4. checking unconstrained_internal_endpoints
--------------------------------------------
There are 130 pins that are not constrained for maximum delay. (HIGH)
There are 0 pins that are not constrained for maximum delay due to constant clock.
5. checking no_input_delay
--------------------------
There is 1 input port with no input delay specified. (HIGH)
There are 0 input ports with no input delay but user has a false path constraint.
6. checking no_output_delay
---------------------------
There are 22 ports with no output delay specified. (HIGH)
There are 0 ports with no output delay but user has a false path constraint
There are 0 ports with no output delay but with a timing clock defined on it or propagating through it
7. checking multiple_clock
--------------------------
There are 0 register/latch pins with multiple clocks.
8. checking generated_clocks
----------------------------
There are 0 generated clocks that are not connected to a clock source.
9. checking loops
-----------------
There are 0 combinational loops in the design.
10. checking partial_input_delay
--------------------------------
There are 0 input ports with partial input delay specified.
11. checking partial_output_delay
---------------------------------
There are 0 ports with partial output delay specified.
12. checking latch_loops
------------------------
There are 0 combinational latch loops in the design through latch input
------------------------------------------------------------------------------------------------
| Design Timing Summary
| ---------------------
------------------------------------------------------------------------------------------------
WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints
------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- --------------------
NA NA NA NA NA NA NA NA NA NA NA NA
There are no user specified timing constraints.
------------------------------------------------------------------------------------------------
| Clock Summary
| -------------
------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------
| Intra Clock Table
| -----------------
------------------------------------------------------------------------------------------------
Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints
----- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- --------------------
------------------------------------------------------------------------------------------------
| Inter Clock Table
| -----------------
------------------------------------------------------------------------------------------------
From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints
---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- -------------------
------------------------------------------------------------------------------------------------
| Other Path Groups Table
| -----------------------
------------------------------------------------------------------------------------------------
Path Group From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints
---------- ---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- -------------------
------------------------------------------------------------------------------------------------
| Timing Details
| --------------
------------------------------------------------------------------------------------------------

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Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
---------------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2018.1 (win64) Build 2188600 Wed Apr 4 18:40:38 MDT 2018
| Date : Thu Dec 19 03:43:21 2024
| Host : WIN-P8FUKGQFPK3 running 64-bit major release (build 9200)
| Command : report_utilization -file t_date_utilization_placed.rpt -pb t_date_utilization_placed.pb
| Design : t_date
| Device : 7a35tcsg324-1
| Design State : Fully Placed
---------------------------------------------------------------------------------------------------------
Utilization Design Information
Table of Contents
-----------------
1. Slice Logic
1.1 Summary of Registers by Type
2. Slice Logic Distribution
3. Memory
4. DSP
5. IO and GT Specific
6. Clocking
7. Specific Feature
8. Primitives
9. Black Boxes
10. Instantiated Netlists
1. Slice Logic
--------------
+-------------------------+------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+-------------------------+------+-------+-----------+-------+
| Slice LUTs | 63 | 0 | 20800 | 0.30 |
| LUT as Logic | 63 | 0 | 20800 | 0.30 |
| LUT as Memory | 0 | 0 | 9600 | 0.00 |
| Slice Registers | 65 | 0 | 41600 | 0.16 |
| Register as Flip Flop | 65 | 0 | 41600 | 0.16 |
| Register as Latch | 0 | 0 | 41600 | 0.00 |
| F7 Muxes | 0 | 0 | 16300 | 0.00 |
| F8 Muxes | 0 | 0 | 8150 | 0.00 |
+-------------------------+------+-------+-----------+-------+
1.1 Summary of Registers by Type
--------------------------------
+-------+--------------+-------------+--------------+
| Total | Clock Enable | Synchronous | Asynchronous |
+-------+--------------+-------------+--------------+
| 0 | _ | - | - |
| 0 | _ | - | Set |
| 0 | _ | - | Reset |
| 0 | _ | Set | - |
| 0 | _ | Reset | - |
| 0 | Yes | - | - |
| 0 | Yes | - | Set |
| 43 | Yes | - | Reset |
| 1 | Yes | Set | - |
| 21 | Yes | Reset | - |
+-------+--------------+-------------+--------------+
2. Slice Logic Distribution
---------------------------
+-------------------------------------------+------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+-------------------------------------------+------+-------+-----------+-------+
| Slice | 29 | 0 | 8150 | 0.36 |
| SLICEL | 20 | 0 | | |
| SLICEM | 9 | 0 | | |
| LUT as Logic | 63 | 0 | 20800 | 0.30 |
| using O5 output only | 0 | | | |
| using O6 output only | 43 | | | |
| using O5 and O6 | 20 | | | |
| LUT as Memory | 0 | 0 | 9600 | 0.00 |
| LUT as Distributed RAM | 0 | 0 | | |
| LUT as Shift Register | 0 | 0 | | |
| LUT Flip Flop Pairs | 39 | 0 | 20800 | 0.19 |
| fully used LUT-FF pairs | 19 | | | |
| LUT-FF pairs with one unused LUT output | 20 | | | |
| LUT-FF pairs with one unused Flip Flop | 15 | | | |
| Unique Control Sets | 5 | | | |
+-------------------------------------------+------+-------+-----------+-------+
* Note: Review the Control Sets Report for more information regarding control sets.
3. Memory
---------
+----------------+------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+----------------+------+-------+-----------+-------+
| Block RAM Tile | 0 | 0 | 50 | 0.00 |
| RAMB36/FIFO* | 0 | 0 | 50 | 0.00 |
| RAMB18 | 0 | 0 | 100 | 0.00 |
+----------------+------+-------+-----------+-------+
* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1
4. DSP
------
+-----------+------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+-----------+------+-------+-----------+-------+
| DSPs | 0 | 0 | 90 | 0.00 |
+-----------+------+-------+-----------+-------+
5. IO and GT Specific
---------------------
+-----------------------------+------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+-----------------------------+------+-------+-----------+-------+
| Bonded IOB | 26 | 26 | 210 | 12.38 |
| IOB Master Pads | 13 | | | |
| IOB Slave Pads | 13 | | | |
| Bonded IPADs | 0 | 0 | 2 | 0.00 |
| PHY_CONTROL | 0 | 0 | 5 | 0.00 |
| PHASER_REF | 0 | 0 | 5 | 0.00 |
| OUT_FIFO | 0 | 0 | 20 | 0.00 |
| IN_FIFO | 0 | 0 | 20 | 0.00 |
| IDELAYCTRL | 0 | 0 | 5 | 0.00 |
| IBUFDS | 0 | 0 | 202 | 0.00 |
| PHASER_OUT/PHASER_OUT_PHY | 0 | 0 | 20 | 0.00 |
| PHASER_IN/PHASER_IN_PHY | 0 | 0 | 20 | 0.00 |
| IDELAYE2/IDELAYE2_FINEDELAY | 0 | 0 | 250 | 0.00 |
| ILOGIC | 0 | 0 | 210 | 0.00 |
| OLOGIC | 0 | 0 | 210 | 0.00 |
+-----------------------------+------+-------+-----------+-------+
6. Clocking
-----------
+------------+------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+------------+------+-------+-----------+-------+
| BUFGCTRL | 1 | 0 | 32 | 3.13 |
| BUFIO | 0 | 0 | 20 | 0.00 |
| MMCME2_ADV | 0 | 0 | 5 | 0.00 |
| PLLE2_ADV | 0 | 0 | 5 | 0.00 |
| BUFMRCE | 0 | 0 | 10 | 0.00 |
| BUFHCE | 0 | 0 | 72 | 0.00 |
| BUFR | 0 | 0 | 20 | 0.00 |
+------------+------+-------+-----------+-------+
7. Specific Feature
-------------------
+-------------+------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+-------------+------+-------+-----------+-------+
| BSCANE2 | 0 | 0 | 4 | 0.00 |
| CAPTUREE2 | 0 | 0 | 1 | 0.00 |
| DNA_PORT | 0 | 0 | 1 | 0.00 |
| EFUSE_USR | 0 | 0 | 1 | 0.00 |
| FRAME_ECCE2 | 0 | 0 | 1 | 0.00 |
| ICAPE2 | 0 | 0 | 2 | 0.00 |
| PCIE_2_1 | 0 | 0 | 1 | 0.00 |
| STARTUPE2 | 0 | 0 | 1 | 0.00 |
| XADC | 0 | 0 | 1 | 0.00 |
+-------------+------+-------+-----------+-------+
8. Primitives
-------------
+----------+------+---------------------+
| Ref Name | Used | Functional Category |
+----------+------+---------------------+
| FDCE | 43 | Flop & Latch |
| LUT2 | 41 | LUT |
| OBUF | 24 | IO |
| FDRE | 21 | Flop & Latch |
| LUT6 | 18 | LUT |
| CARRY4 | 10 | CarryLogic |
| LUT4 | 9 | LUT |
| LUT5 | 7 | LUT |
| LUT3 | 5 | LUT |
| LUT1 | 3 | LUT |
| IBUF | 2 | IO |
| FDSE | 1 | Flop & Latch |
| BUFG | 1 | Clock |
+----------+------+---------------------+
9. Black Boxes
--------------
+----------+------+
| Ref Name | Used |
+----------+------+
10. Instantiated Netlists
-------------------------
+----------+------+
| Ref Name | Used |
+----------+------+

631
test/test.runs/impl_1/usage_statistics_webtalk.xml Normal file
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<keyValuePair key="bufhce_available" value="72" description="" />
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<keyValuePair key="bufhce_util_percentage" value="0.00" description="" />
<keyValuePair key="bufio_available" value="20" description="" />
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<keyValuePair key="bufmrce_available" value="10" description="" />
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<keyValuePair key="bufr_available" value="20" description="" />
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<keyValuePair key="bufr_util_percentage" value="0.00" description="" />
<keyValuePair key="mmcme2_adv_available" value="5" description="" />
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<keyValuePair key="plle2_adv_available" value="5" description="" />
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<keyValuePair key="plle2_adv_used" value="0" description="" />
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</section>
<section name="dsp" level="2" order="2" description="">
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<keyValuePair key="dsps_used" value="0" description="" />
<keyValuePair key="dsps_util_percentage" value="0.00" description="" />
</section>
<section name="io_standard" level="2" order="3" description="">
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<keyValuePair key="diff_hstl_i" value="0" description="" />
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<keyValuePair key="hstl_i" value="0" description="" />
<keyValuePair key="hstl_i_18" value="0" description="" />
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<keyValuePair key="hstl_ii_18" value="0" description="" />
<keyValuePair key="hsul_12" value="0" description="" />
<keyValuePair key="lvcmos12" value="0" description="" />
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<keyValuePair key="lvds_25" value="0" description="" />
<keyValuePair key="lvttl" value="0" description="" />
<keyValuePair key="mini_lvds_25" value="0" description="" />
<keyValuePair key="mobile_ddr" value="0" description="" />
<keyValuePair key="pci33_3" value="0" description="" />
<keyValuePair key="ppds_25" value="0" description="" />
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<keyValuePair key="sstl135" value="0" description="" />
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<keyValuePair key="sstl18_ii" value="0" description="" />
<keyValuePair key="tmds_33" value="0" description="" />
</section>
<section name="memory" level="2" order="4" description="">
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<keyValuePair key="block_ram_tile_fixed" value="0" description="" />
<keyValuePair key="block_ram_tile_used" value="0" description="" />
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<keyValuePair key="ramb18_available" value="100" description="" />
<keyValuePair key="ramb18_fixed" value="0" description="" />
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<keyValuePair key="ramb18_util_percentage" value="0.00" description="" />
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<keyValuePair key="ramb36_fifo_util_percentage" value="0.00" description="" />
</section>
<section name="primitives" level="2" order="5" description="">
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<keyValuePair key="bufg_used" value="1" description="" />
<keyValuePair key="carry4_functional_category" value="CarryLogic" description="" />
<keyValuePair key="carry4_used" value="10" description="" />
<keyValuePair key="fdce_functional_category" value="Flop &amp; Latch" description="" />
<keyValuePair key="fdce_used" value="43" description="" />
<keyValuePair key="fdre_functional_category" value="Flop &amp; Latch" description="" />
<keyValuePair key="fdre_used" value="21" description="" />
<keyValuePair key="fdse_functional_category" value="Flop &amp; Latch" description="" />
<keyValuePair key="fdse_used" value="1" description="" />
<keyValuePair key="ibuf_functional_category" value="IO" description="" />
<keyValuePair key="ibuf_used" value="2" description="" />
<keyValuePair key="lut1_functional_category" value="LUT" description="" />
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<keyValuePair key="lut2_functional_category" value="LUT" description="" />
<keyValuePair key="lut2_used" value="41" description="" />
<keyValuePair key="lut3_functional_category" value="LUT" description="" />
<keyValuePair key="lut3_used" value="5" description="" />
<keyValuePair key="lut4_functional_category" value="LUT" description="" />
<keyValuePair key="lut4_used" value="9" description="" />
<keyValuePair key="lut5_functional_category" value="LUT" description="" />
<keyValuePair key="lut5_used" value="7" description="" />
<keyValuePair key="lut6_functional_category" value="LUT" description="" />
<keyValuePair key="lut6_used" value="18" description="" />
<keyValuePair key="obuf_functional_category" value="IO" description="" />
<keyValuePair key="obuf_used" value="24" description="" />
</section>
<section name="slice_logic" level="2" order="6" description="">
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<keyValuePair key="f7_muxes_used" value="0" description="" />
<keyValuePair key="f7_muxes_util_percentage" value="0.00" description="" />
<keyValuePair key="f8_muxes_available" value="8150" description="" />
<keyValuePair key="f8_muxes_fixed" value="0" description="" />
<keyValuePair key="f8_muxes_used" value="0" description="" />
<keyValuePair key="f8_muxes_util_percentage" value="0.00" description="" />
<keyValuePair key="fully_used_lut_ff_pairs_fixed" value="0.16" description="" />
<keyValuePair key="fully_used_lut_ff_pairs_used" value="19" description="" />
<keyValuePair key="lut_as_distributed_ram_fixed" value="0" description="" />
<keyValuePair key="lut_as_distributed_ram_used" value="0" description="" />
<keyValuePair key="lut_as_logic_available" value="20800" description="" />
<keyValuePair key="lut_as_logic_available" value="20800" description="" />
<keyValuePair key="lut_as_logic_fixed" value="0" description="" />
<keyValuePair key="lut_as_logic_fixed" value="0" description="" />
<keyValuePair key="lut_as_logic_used" value="63" description="" />
<keyValuePair key="lut_as_logic_used" value="63" description="" />
<keyValuePair key="lut_as_logic_util_percentage" value="0.30" description="" />
<keyValuePair key="lut_as_logic_util_percentage" value="0.30" description="" />
<keyValuePair key="lut_as_memory_available" value="9600" description="" />
<keyValuePair key="lut_as_memory_available" value="9600" description="" />
<keyValuePair key="lut_as_memory_fixed" value="0" description="" />
<keyValuePair key="lut_as_memory_fixed" value="0" description="" />
<keyValuePair key="lut_as_memory_used" value="0" description="" />
<keyValuePair key="lut_as_memory_used" value="0" description="" />
<keyValuePair key="lut_as_memory_util_percentage" value="0.00" description="" />
<keyValuePair key="lut_as_memory_util_percentage" value="0.00" description="" />
<keyValuePair key="lut_as_shift_register_fixed" value="0" description="" />
<keyValuePair key="lut_as_shift_register_used" value="0" description="" />
<keyValuePair key="lut_ff_pairs_with_one_unused_flip_flop_fixed" value="0" description="" />
<keyValuePair key="lut_ff_pairs_with_one_unused_flip_flop_used" value="15" description="" />
<keyValuePair key="lut_ff_pairs_with_one_unused_lut_output_fixed" value="15" description="" />
<keyValuePair key="lut_ff_pairs_with_one_unused_lut_output_used" value="20" description="" />
<keyValuePair key="lut_flip_flop_pairs_available" value="20800" description="" />
<keyValuePair key="lut_flip_flop_pairs_fixed" value="0" description="" />
<keyValuePair key="lut_flip_flop_pairs_used" value="39" description="" />
<keyValuePair key="lut_flip_flop_pairs_util_percentage" value="0.19" description="" />
<keyValuePair key="register_as_flip_flop_available" value="41600" description="" />
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<keyValuePair key="register_as_flip_flop_util_percentage" value="0.16" description="" />
<keyValuePair key="register_as_latch_available" value="41600" description="" />
<keyValuePair key="register_as_latch_fixed" value="0" description="" />
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<keyValuePair key="register_as_latch_util_percentage" value="0.00" description="" />
<keyValuePair key="slice_available" value="8150" description="" />
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<keyValuePair key="slice_luts_available" value="20800" description="" />
<keyValuePair key="slice_luts_fixed" value="0" description="" />
<keyValuePair key="slice_luts_used" value="63" description="" />
<keyValuePair key="slice_luts_util_percentage" value="0.30" description="" />
<keyValuePair key="slice_registers_available" value="41600" description="" />
<keyValuePair key="slice_registers_fixed" value="0" description="" />
<keyValuePair key="slice_registers_used" value="65" description="" />
<keyValuePair key="slice_registers_util_percentage" value="0.16" description="" />
<keyValuePair key="slice_used" value="29" description="" />
<keyValuePair key="slice_util_percentage" value="0.36" description="" />
<keyValuePair key="slicel_fixed" value="0" description="" />
<keyValuePair key="slicel_used" value="20" description="" />
<keyValuePair key="slicem_fixed" value="0" description="" />
<keyValuePair key="slicem_used" value="9" description="" />
<keyValuePair key="unique_control_sets_used" value="5" description="" />
<keyValuePair key="using_o5_and_o6_fixed" value="5" description="" />
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<keyValuePair key="using_o6_output_only_used" value="43" description="" />
</section>
<section name="specific_feature" level="2" order="7" description="">
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<keyValuePair key="bscane2_used" value="0" description="" />
<keyValuePair key="bscane2_util_percentage" value="0.00" description="" />
<keyValuePair key="capturee2_available" value="1" description="" />
<keyValuePair key="capturee2_fixed" value="0" description="" />
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<keyValuePair key="capturee2_util_percentage" value="0.00" description="" />
<keyValuePair key="dna_port_available" value="1" description="" />
<keyValuePair key="dna_port_fixed" value="0" description="" />
<keyValuePair key="dna_port_used" value="0" description="" />
<keyValuePair key="dna_port_util_percentage" value="0.00" description="" />
<keyValuePair key="efuse_usr_available" value="1" description="" />
<keyValuePair key="efuse_usr_fixed" value="0" description="" />
<keyValuePair key="efuse_usr_used" value="0" description="" />
<keyValuePair key="efuse_usr_util_percentage" value="0.00" description="" />
<keyValuePair key="frame_ecce2_available" value="1" description="" />
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<keyValuePair key="frame_ecce2_util_percentage" value="0.00" description="" />
<keyValuePair key="icape2_available" value="2" description="" />
<keyValuePair key="icape2_fixed" value="0" description="" />
<keyValuePair key="icape2_used" value="0" description="" />
<keyValuePair key="icape2_util_percentage" value="0.00" description="" />
<keyValuePair key="pcie_2_1_available" value="1" description="" />
<keyValuePair key="pcie_2_1_fixed" value="0" description="" />
<keyValuePair key="pcie_2_1_used" value="0" description="" />
<keyValuePair key="pcie_2_1_util_percentage" value="0.00" description="" />
<keyValuePair key="startupe2_available" value="1" description="" />
<keyValuePair key="startupe2_fixed" value="0" description="" />
<keyValuePair key="startupe2_used" value="0" description="" />
<keyValuePair key="startupe2_util_percentage" value="0.00" description="" />
<keyValuePair key="xadc_available" value="1" description="" />
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<keyValuePair key="xadc_used" value="0" description="" />
<keyValuePair key="xadc_util_percentage" value="0.00" description="" />
</section>
</section>
<section name="router" level="1" order="7" description="">
<section name="usage" level="2" order="1" description="">
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<keyValuePair key="bogomips" value="0" description="" />
<keyValuePair key="bram18" value="0" description="" />
<keyValuePair key="bram36" value="0" description="" />
<keyValuePair key="bufg" value="0" description="" />
<keyValuePair key="bufr" value="0" description="" />
<keyValuePair key="ctrls" value="5" description="" />
<keyValuePair key="dsp" value="0" description="" />
<keyValuePair key="effort" value="2" description="" />
<keyValuePair key="estimated_expansions" value="91494" description="" />
<keyValuePair key="ff" value="65" description="" />
<keyValuePair key="global_clocks" value="1" description="" />
<keyValuePair key="high_fanout_nets" value="0" description="" />
<keyValuePair key="iob" value="26" description="" />
<keyValuePair key="lut" value="63" description="" />
<keyValuePair key="movable_instances" value="189" description="" />
<keyValuePair key="nets" value="225" description="" />
<keyValuePair key="pins" value="925" description="" />
<keyValuePair key="pll" value="0" description="" />
<keyValuePair key="router_runtime" value="0.000000" description="" />
<keyValuePair key="router_timing_driven" value="1" description="" />
<keyValuePair key="threads" value="2" description="" />
<keyValuePair key="timing_constraints_exist" value="1" description="" />
</section>
</section>
<section name="synthesis" level="1" order="8" description="">
<section name="command_line_options" level="2" order="1" description="">
<keyValuePair key="-assert" value="default::[not_specified]" description="" />
<keyValuePair key="-bufg" value="default::12" description="" />
<keyValuePair key="-cascade_dsp" value="default::auto" description="" />
<keyValuePair key="-constrset" value="default::[not_specified]" description="" />
<keyValuePair key="-control_set_opt_threshold" value="default::auto" description="" />
<keyValuePair key="-directive" value="default::default" description="" />
<keyValuePair key="-fanout_limit" value="default::10000" description="" />
<keyValuePair key="-flatten_hierarchy" value="default::rebuilt" description="" />
<keyValuePair key="-fsm_extraction" value="default::auto" description="" />
<keyValuePair key="-gated_clock_conversion" value="default::off" description="" />
<keyValuePair key="-generic" value="default::[not_specified]" description="" />
<keyValuePair key="-include_dirs" value="default::[not_specified]" description="" />
<keyValuePair key="-keep_equivalent_registers" value="default::[not_specified]" description="" />
<keyValuePair key="-max_bram" value="default::-1" description="" />
<keyValuePair key="-max_bram_cascade_height" value="default::-1" description="" />
<keyValuePair key="-max_dsp" value="default::-1" description="" />
<keyValuePair key="-max_uram" value="default::-1" description="" />
<keyValuePair key="-max_uram_cascade_height" value="default::-1" description="" />
<keyValuePair key="-mode" value="default::default" description="" />
<keyValuePair key="-name" value="default::[not_specified]" description="" />
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<keyValuePair key="-top" value="t_date" description="" />
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</section>
<section name="usage" level="2" order="2" description="">
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</section>
</section>
<section name="unisim_transformation" level="1" order="9" description="">
<section name="post_unisim_transformation" level="2" order="1" description="">
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</section>
<section name="pre_unisim_transformation" level="2" order="2" description="">
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<keyValuePair key="obuf" value="24" description="" />
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</section>
</section>
<section name="vivado_usage" level="1" order="10" description="">
<section name="gui_handlers" level="2" order="1" description="">
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<keyValuePair key="rdicommands_custom_commands" value="1" description="" />
<keyValuePair key="rdicommands_settings" value="1" description="" />
<keyValuePair key="saveprojectutils_cancel" value="1" description="" />
<keyValuePair key="settingsdialog_options_tree" value="7" description="" />
<keyValuePair key="settingsthemepanel_select_colors_and_font_that_have" value="2" description="" />
<keyValuePair key="srcchooserpanel_add_hdl_and_netlist_files_to_your_project" value="2" description="" />
<keyValuePair key="srcchooserpanel_make_local_copy_of_these_files_into" value="1" description="" />
<keyValuePair key="syntheticagettingstartedview_recent_projects" value="2" description="" />
<keyValuePair key="taskbanner_close" value="3" description="" />
<keyValuePair key="touchpointsurveydialog_no" value="1" description="" />
</section>
<section name="java_command_handlers" level="2" order="2" description="">
<keyValuePair key="addsources" value="3" description="" />
<keyValuePair key="addxvctarget" value="2" description="" />
<keyValuePair key="autoconnecttarget" value="10" description="" />
<keyValuePair key="closeproject" value="1" description="" />
<keyValuePair key="launchopentarget" value="1" description="" />
<keyValuePair key="launchprogramfpga" value="10" description="" />
<keyValuePair key="newproject" value="1" description="" />
<keyValuePair key="openhardwaremanager" value="6" description="" />
<keyValuePair key="openproject" value="1" description="" />
<keyValuePair key="opentarget" value="1" description="" />
<keyValuePair key="refreshserver" value="5" description="" />
<keyValuePair key="runbitgen" value="12" description="" />
<keyValuePair key="showview" value="1" description="" />
<keyValuePair key="toolssettings" value="1" description="" />
</section>
<section name="other_data" level="2" order="3" description="">
<keyValuePair key="guimode" value="4" description="" />
</section>
<section name="project_data" level="2" order="4" description="">
<keyValuePair key="constraintsetcount" value="1" description="" />
<keyValuePair key="core_container" value="false" description="" />
<keyValuePair key="currentimplrun" value="impl_1" description="" />
<keyValuePair key="currentsynthesisrun" value="synth_1" description="" />
<keyValuePair key="default_library" value="xil_defaultlib" description="" />
<keyValuePair key="designmode" value="RTL" description="" />
<keyValuePair key="export_simulation_activehdl" value="0" description="" />
<keyValuePair key="export_simulation_ies" value="0" description="" />
<keyValuePair key="export_simulation_modelsim" value="0" description="" />
<keyValuePair key="export_simulation_questa" value="0" description="" />
<keyValuePair key="export_simulation_riviera" value="0" description="" />
<keyValuePair key="export_simulation_vcs" value="0" description="" />
<keyValuePair key="export_simulation_xsim" value="0" description="" />
<keyValuePair key="implstrategy" value="Vivado Implementation Defaults" description="" />
<keyValuePair key="launch_simulation_activehdl" value="0" description="" />
<keyValuePair key="launch_simulation_ies" value="0" description="" />
<keyValuePair key="launch_simulation_modelsim" value="0" description="" />
<keyValuePair key="launch_simulation_questa" value="0" description="" />
<keyValuePair key="launch_simulation_riviera" value="0" description="" />
<keyValuePair key="launch_simulation_vcs" value="0" description="" />
<keyValuePair key="launch_simulation_xsim" value="0" description="" />
<keyValuePair key="simulator_language" value="Mixed" description="" />
<keyValuePair key="srcsetcount" value="3" description="" />
<keyValuePair key="synthesisstrategy" value="Vivado Synthesis Defaults" description="" />
<keyValuePair key="target_language" value="Verilog" description="" />
<keyValuePair key="target_simulator" value="XSim" description="" />
<keyValuePair key="totalimplruns" value="1" description="" />
<keyValuePair key="totalsynthesisruns" value="1" description="" />
</section>
</section>
</section>
</webTalkData>

12
test/test.runs/impl_1/vivado.jou Normal file
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#-----------------------------------------------------------
# Vivado v2018.1 (64-bit)
# SW Build 2188600 on Wed Apr 4 18:40:38 MDT 2018
# IP Build 2185939 on Wed Apr 4 20:55:05 MDT 2018
# Start of session at: Thu Dec 19 03:42:56 2024
# Process ID: 4648
# Current directory: Z:/Storage/Schoolwork/DigitalLogic/test/test.runs/impl_1
# Command line: vivado.exe -log t_date.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source t_date.tcl -notrace
# Log file: Z:/Storage/Schoolwork/DigitalLogic/test/test.runs/impl_1/t_date.vdi
# Journal file: Z:/Storage/Schoolwork/DigitalLogic/test/test.runs/impl_1\vivado.jou
#-----------------------------------------------------------
source t_date.tcl -notrace

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test/test.runs/synth_1/.Xil/t_date_propImpl.xdc Normal file
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set_property SRC_FILE_INFO {cfile:Z:/Storage/Schoolwork/DigitalLogic/test/test.srcs/constrs_1/imports/Downloads/EX1.xdc rfile:../../../test.srcs/constrs_1/imports/Downloads/EX1.xdc id:1} [current_design]
set_property src_info {type:XDC file:1 line:27 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN P17 [get_ports clk]
set_property src_info {type:XDC file:1 line:28 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN R15 [get_ports rst]
set_property src_info {type:XDC file:1 line:29 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN B4 [get_ports {a_h1[7]}]
set_property src_info {type:XDC file:1 line:30 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN A4 [get_ports {a_h1[6]}]
set_property src_info {type:XDC file:1 line:31 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN A3 [get_ports {a_h1[5]}]
set_property src_info {type:XDC file:1 line:32 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN B1 [get_ports {a_h1[4]}]
set_property src_info {type:XDC file:1 line:33 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN A1 [get_ports {a_h1[3]}]
set_property src_info {type:XDC file:1 line:34 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN B3 [get_ports {a_h1[2]}]
set_property src_info {type:XDC file:1 line:35 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN B2 [get_ports {a_h1[1]}]
set_property src_info {type:XDC file:1 line:36 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN D5 [get_ports {a_h1[0]}]
set_property src_info {type:XDC file:1 line:37 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN D4 [get_ports {a_h2[7]}]
set_property src_info {type:XDC file:1 line:38 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN E3 [get_ports {a_h2[6]}]
set_property src_info {type:XDC file:1 line:39 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN D3 [get_ports {a_h2[5]}]
set_property src_info {type:XDC file:1 line:40 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN F4 [get_ports {a_h2[4]}]
set_property src_info {type:XDC file:1 line:41 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN F3 [get_ports {a_h2[3]}]
set_property src_info {type:XDC file:1 line:42 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN E2 [get_ports {a_h2[2]}]
set_property src_info {type:XDC file:1 line:43 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN D2 [get_ports {a_h2[1]}]
set_property src_info {type:XDC file:1 line:44 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN H2 [get_ports {a_h2[0]}]
set_property src_info {type:XDC file:1 line:45 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN G2 [get_ports {an[7]}]
set_property src_info {type:XDC file:1 line:46 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN C2 [get_ports {an[6]}]
set_property src_info {type:XDC file:1 line:47 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN C1 [get_ports {an[5]}]
set_property src_info {type:XDC file:1 line:48 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN H1 [get_ports {an[4]}]
set_property src_info {type:XDC file:1 line:49 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN G1 [get_ports {an[3]}]
set_property src_info {type:XDC file:1 line:50 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN F1 [get_ports {an[2]}]
set_property src_info {type:XDC file:1 line:51 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN E1 [get_ports {an[1]}]
set_property src_info {type:XDC file:1 line:52 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN G6 [get_ports {an[0]}]

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test/test.runs/synth_1/gen_run.xml Normal file
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<?xml version="1.0" encoding="UTF-8"?>
<GenRun Id="synth_1" LaunchPart="xc7a35tcsg324-1" LaunchTime="1734550937">
<File Type="PA-TCL" Name="t_date.tcl"/>
<File Type="RDS-PROPCONSTRS" Name="t_date_drc_synth.rpt"/>
<File Type="REPORTS-TCL" Name="t_date_reports.tcl"/>
<File Type="RDS-RDS" Name="t_date.vds"/>
<File Type="RDS-UTIL" Name="t_date_utilization_synth.rpt"/>
<File Type="RDS-UTIL-PB" Name="t_date_utilization_synth.pb"/>
<File Type="RDS-DCP" Name="t_date.dcp"/>
<File Type="VDS-TIMINGSUMMARY" Name="t_date_timing_summary_synth.rpt"/>
<File Type="VDS-TIMING-PB" Name="t_date_timing_summary_synth.pb"/>
<FileSet Name="sources" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1">
<Filter Type="Srcs"/>
<File Path="$PSRCDIR/sources_1/imports/Downloads/slow.v">
<FileInfo>
<Attr Name="ImportPath" Val="$PPRDIR/../../../Downloads/slow.v"/>
<Attr Name="ImportTime" Val="1734532876"/>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/imports/Downloads/t_date.v">
<FileInfo>
<Attr Name="ImportPath" Val="$PPRDIR/../../../Downloads/t_date.v"/>
<Attr Name="ImportTime" Val="1734443575"/>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/imports/Downloads/OUT.v">
<FileInfo>
<Attr Name="AutoDisabled" Val="1"/>
<Attr Name="ImportPath" Val="$PPRDIR/../../../Downloads/OUT.v"/>
<Attr Name="ImportTime" Val="1734532870"/>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<Config>
<Option Name="DesignMode" Val="RTL"/>
<Option Name="TopModule" Val="t_date"/>
<Option Name="TopAutoSet" Val="TRUE"/>
</Config>
</FileSet>
<FileSet Name="constrs_in" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1">
<Filter Type="Constrs"/>
<File Path="$PSRCDIR/constrs_1/imports/Downloads/EX1.xdc">
<FileInfo>
<Attr Name="ImportPath" Val="$PPRDIR/../../../Downloads/EX1.xdc"/>
<Attr Name="ImportTime" Val="1734529765"/>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
</FileInfo>
</File>
<Config>
<Option Name="ConstrsType" Val="XDC"/>
</Config>
</FileSet>
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2018"/>
<Step Id="synth_design"/>
</Strategy>
</GenRun>

9
test/test.runs/synth_1/htr.txt Normal file
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REM
REM Vivado(TM)
REM htr.txt: a Vivado-generated description of how-to-repeat the
REM the basic steps of a run. Note that runme.bat/sh needs
REM to be invoked for Vivado to track run status.
REM Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
REM
vivado -log t_date.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source t_date.tcl

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test/test.runs/synth_1/t_date.dcp Normal file
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57
test/test.runs/synth_1/t_date.tcl Normal file
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#
# Synthesis run script generated by Vivado
#
proc create_report { reportName command } {
set status "."
append status $reportName ".fail"
if { [file exists $status] } {
eval file delete [glob $status]
}
send_msg_id runtcl-4 info "Executing : $command"
set retval [eval catch { $command } msg]
if { $retval != 0 } {
set fp [open $status w]
close $fp
send_msg_id runtcl-5 warning "$msg"
}
}
set_param xicom.use_bs_reader 1
create_project -in_memory -part xc7a35tcsg324-1
set_param project.singleFileAddWarning.threshold 0
set_param project.compositeFile.enableAutoGeneration 0
set_param synth.vivado.isSynthRun true
set_property webtalk.parent_dir Z:/Storage/Schoolwork/DigitalLogic/test/test.cache/wt [current_project]
set_property parent.project_path Z:/Storage/Schoolwork/DigitalLogic/test/test.xpr [current_project]
set_property default_lib xil_defaultlib [current_project]
set_property target_language Verilog [current_project]
set_property ip_output_repo z:/Storage/Schoolwork/DigitalLogic/test/test.cache/ip [current_project]
set_property ip_cache_permissions {read write} [current_project]
read_verilog -library xil_defaultlib {
Z:/Storage/Schoolwork/DigitalLogic/test/test.srcs/sources_1/imports/Downloads/slow.v
Z:/Storage/Schoolwork/DigitalLogic/test/test.srcs/sources_1/imports/Downloads/t_date.v
}
# Mark all dcp files as not used in implementation to prevent them from being
# stitched into the results of this synthesis run. Any black boxes in the
# design are intentionally left as such for best results. Dcp files will be
# stitched into the design at a later time, either when this synthesis run is
# opened, or when it is stitched into a dependent implementation run.
foreach dcp [get_files -quiet -all -filter file_type=="Design\ Checkpoint"] {
set_property used_in_implementation false $dcp
}
read_xdc Z:/Storage/Schoolwork/DigitalLogic/test/test.srcs/constrs_1/imports/Downloads/EX1.xdc
set_property used_in_implementation false [get_files Z:/Storage/Schoolwork/DigitalLogic/test/test.srcs/constrs_1/imports/Downloads/EX1.xdc]
set_param ips.enableIPCacheLiteLoad 0
close [open __synthesis_is_running__ w]
synth_design -top t_date -part xc7a35tcsg324-1
# disable binary constraint mode for synth run checkpoints
set_param constraints.enableBinaryConstraints false
write_checkpoint -force -noxdef t_date.dcp
create_report "synth_1_synth_report_utilization_0" "report_utilization -file t_date_utilization_synth.rpt -pb t_date_utilization_synth.pb"
file delete __synthesis_is_running__
close [open __synthesis_is_complete__ w]

403
test/test.runs/synth_1/t_date.vds Normal file
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#-----------------------------------------------------------
# Vivado v2018.1 (64-bit)
# SW Build 2188600 on Wed Apr 4 18:40:38 MDT 2018
# IP Build 2185939 on Wed Apr 4 20:55:05 MDT 2018
# Start of session at: Thu Dec 19 03:42:19 2024
# Process ID: 3132
# Current directory: Z:/Storage/Schoolwork/DigitalLogic/test/test.runs/synth_1
# Command line: vivado.exe -log t_date.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source t_date.tcl
# Log file: Z:/Storage/Schoolwork/DigitalLogic/test/test.runs/synth_1/t_date.vds
# Journal file: Z:/Storage/Schoolwork/DigitalLogic/test/test.runs/synth_1\vivado.jou
#-----------------------------------------------------------
source t_date.tcl -notrace
Command: synth_design -top t_date -part xc7a35tcsg324-1
Starting synth_design
Attempting to get a license for feature 'Synthesis' and/or device 'xc7a35t'
INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7a35t'
INFO: Launching helper process for spawning children vivado processes
INFO: Helper process launched with PID 692
---------------------------------------------------------------------------------
Starting RTL Elaboration : Time (s): cpu = 00:00:02 ; elapsed = 00:00:04 . Memory (MB): peak = 407.832 ; gain = 96.258
---------------------------------------------------------------------------------
INFO: [Synth 8-6157] synthesizing module 't_date' [Z:/Storage/Schoolwork/DigitalLogic/test/test.srcs/sources_1/imports/Downloads/t_date.v:23]
Parameter y0 bound to: 4'b0000
Parameter y1 bound to: 4'b0001
Parameter y2 bound to: 4'b0010
Parameter y3 bound to: 4'b0011
Parameter y4 bound to: 4'b0100
Parameter y5 bound to: 4'b0101
Parameter y6 bound to: 4'b0110
Parameter y7 bound to: 4'b0111
INFO: [Synth 8-6157] synthesizing module 'clk' [Z:/Storage/Schoolwork/DigitalLogic/test/test.srcs/sources_1/imports/Downloads/slow.v:23]
Parameter sys_clk bound to: 100000000 - type: integer
Parameter clk_out1 bound to: 1 - type: integer
Parameter clk_out20k bound to: 20000 - type: integer
Parameter max1 bound to: 49999999 - type: integer
Parameter max20k bound to: 2499 - type: integer
INFO: [Synth 8-6155] done synthesizing module 'clk' (1#1) [Z:/Storage/Schoolwork/DigitalLogic/test/test.srcs/sources_1/imports/Downloads/slow.v:23]
INFO: [Synth 8-155] case statement is not full and has no default [Z:/Storage/Schoolwork/DigitalLogic/test/test.srcs/sources_1/imports/Downloads/t_date.v:38]
INFO: [Synth 8-155] case statement is not full and has no default [Z:/Storage/Schoolwork/DigitalLogic/test/test.srcs/sources_1/imports/Downloads/t_date.v:57]
INFO: [Synth 8-155] case statement is not full and has no default [Z:/Storage/Schoolwork/DigitalLogic/test/test.srcs/sources_1/imports/Downloads/t_date.v:63]
INFO: [Synth 8-155] case statement is not full and has no default [Z:/Storage/Schoolwork/DigitalLogic/test/test.srcs/sources_1/imports/Downloads/t_date.v:70]
INFO: [Synth 8-155] case statement is not full and has no default [Z:/Storage/Schoolwork/DigitalLogic/test/test.srcs/sources_1/imports/Downloads/t_date.v:78]
INFO: [Synth 8-155] case statement is not full and has no default [Z:/Storage/Schoolwork/DigitalLogic/test/test.srcs/sources_1/imports/Downloads/t_date.v:87]
INFO: [Synth 8-155] case statement is not full and has no default [Z:/Storage/Schoolwork/DigitalLogic/test/test.srcs/sources_1/imports/Downloads/t_date.v:97]
INFO: [Synth 8-155] case statement is not full and has no default [Z:/Storage/Schoolwork/DigitalLogic/test/test.srcs/sources_1/imports/Downloads/t_date.v:108]
INFO: [Synth 8-155] case statement is not full and has no default [Z:/Storage/Schoolwork/DigitalLogic/test/test.srcs/sources_1/imports/Downloads/t_date.v:52]
INFO: [Synth 8-6155] done synthesizing module 't_date' (2#1) [Z:/Storage/Schoolwork/DigitalLogic/test/test.srcs/sources_1/imports/Downloads/t_date.v:23]
---------------------------------------------------------------------------------
Finished RTL Elaboration : Time (s): cpu = 00:00:03 ; elapsed = 00:00:04 . Memory (MB): peak = 463.461 ; gain = 151.887
---------------------------------------------------------------------------------
Report Check Netlist:
+------+------------------+-------+---------+-------+------------------+
| |Item |Errors |Warnings |Status |Description |
+------+------------------+-------+---------+-------+------------------+
|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets |
+------+------------------+-------+---------+-------+------------------+
---------------------------------------------------------------------------------
Start Handling Custom Attributes
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Handling Custom Attributes : Time (s): cpu = 00:00:03 ; elapsed = 00:00:05 . Memory (MB): peak = 463.461 ; gain = 151.887
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:03 ; elapsed = 00:00:05 . Memory (MB): peak = 463.461 ; gain = 151.887
---------------------------------------------------------------------------------
INFO: [Device 21-403] Loading part xc7a35tcsg324-1
INFO: [Project 1-570] Preparing netlist for logic optimization
Processing XDC Constraints
Initializing timing engine
Parsing XDC File [Z:/Storage/Schoolwork/DigitalLogic/test/test.srcs/constrs_1/imports/Downloads/EX1.xdc]
Finished Parsing XDC File [Z:/Storage/Schoolwork/DigitalLogic/test/test.srcs/constrs_1/imports/Downloads/EX1.xdc]
INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [Z:/Storage/Schoolwork/DigitalLogic/test/test.srcs/constrs_1/imports/Downloads/EX1.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/t_date_propImpl.xdc].
Resolution: To avoid this warning, move constraints listed in [.Xil/t_date_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
Completed Processing XDC Constraints
INFO: [Project 1-111] Unisim Transformation Summary:
No Unisim elements were transformed.
Constraint Validation Runtime : Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.004 . Memory (MB): peak = 788.133 ; gain = 0.000
---------------------------------------------------------------------------------
Finished Constraint Validation : Time (s): cpu = 00:00:07 ; elapsed = 00:00:14 . Memory (MB): peak = 788.133 ; gain = 476.559
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Loading Part and Timing Information
---------------------------------------------------------------------------------
Loading part: xc7a35tcsg324-1
---------------------------------------------------------------------------------
Finished Loading Part and Timing Information : Time (s): cpu = 00:00:07 ; elapsed = 00:00:14 . Memory (MB): peak = 788.133 ; gain = 476.559
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Applying 'set_property' XDC Constraints
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:07 ; elapsed = 00:00:14 . Memory (MB): peak = 788.133 ; gain = 476.559
---------------------------------------------------------------------------------
INFO: [Synth 8-5545] ROM "clk_1HZ" won't be mapped to RAM because address size (26) is larger than maximum supported(25)
INFO: [Synth 8-5546] ROM "clk_20kHZ" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-802] inferred FSM for state register 'state_c_reg' in module 't_date'
INFO: [Synth 8-5546] ROM "a_h2" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "a_h2" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "a_h2" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "a_h2" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "a_h2" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "a_h2" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "a_h2" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "a_h1" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "a_h1" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "a_h1" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "a_h1" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5544] ROM "an" won't be mapped to Block RAM because address size (4) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "state_n" won't be mapped to Block RAM because address size (4) smaller than threshold (5)
WARNING: [Synth 8-327] inferring latch for variable 'FSM_sequential_state_n_reg' [Z:/Storage/Schoolwork/DigitalLogic/test/test.srcs/sources_1/imports/Downloads/t_date.v:39]
WARNING: [Synth 8-327] inferring latch for variable 'FSM_onehot_state_n_reg' [Z:/Storage/Schoolwork/DigitalLogic/test/test.srcs/sources_1/imports/Downloads/t_date.v:39]
---------------------------------------------------------------------------------------------------
State | New Encoding | Previous Encoding
---------------------------------------------------------------------------------------------------
iSTATE | 000 | 0000
iSTATE0 | 001 | 0001
iSTATE1 | 010 | 0010
iSTATE2 | 011 | 0011
iSTATE3 | 100 | 0100
iSTATE4 | 101 | 0101
iSTATE5 | 110 | 0110
iSTATE6 | 111 | 0111
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'state_c_reg' using encoding 'sequential' in module 't_date'
WARNING: [Synth 8-327] inferring latch for variable 'FSM_sequential_state_n_reg' [Z:/Storage/Schoolwork/DigitalLogic/test/test.srcs/sources_1/imports/Downloads/t_date.v:39]
---------------------------------------------------------------------------------
Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:07 ; elapsed = 00:00:14 . Memory (MB): peak = 788.133 ; gain = 476.559
---------------------------------------------------------------------------------
Report RTL Partitions:
+-+--------------+------------+----------+
| |RTL Partition |Replication |Instances |
+-+--------------+------------+----------+
+-+--------------+------------+----------+
---------------------------------------------------------------------------------
Start RTL Component Statistics
---------------------------------------------------------------------------------
Detailed RTL Component Info :
+---Adders :
2 Input 26 Bit Adders := 1
2 Input 12 Bit Adders := 1
+---Registers :
26 Bit Registers := 1
12 Bit Registers := 1
8 Bit Registers := 3
1 Bit Registers := 2
+---Muxes :
2 Input 26 Bit Muxes := 1
2 Input 12 Bit Muxes := 1
2 Input 8 Bit Muxes := 6
7 Input 8 Bit Muxes := 2
8 Input 8 Bit Muxes := 6
9 Input 8 Bit Muxes := 2
3 Input 8 Bit Muxes := 1
4 Input 8 Bit Muxes := 1
5 Input 8 Bit Muxes := 1
6 Input 8 Bit Muxes := 1
8 Input 3 Bit Muxes := 1
2 Input 1 Bit Muxes := 11
6 Input 1 Bit Muxes := 2
7 Input 1 Bit Muxes := 2
8 Input 1 Bit Muxes := 4
9 Input 1 Bit Muxes := 2
3 Input 1 Bit Muxes := 1
4 Input 1 Bit Muxes := 1
5 Input 1 Bit Muxes := 1
---------------------------------------------------------------------------------
Finished RTL Component Statistics
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start RTL Hierarchical Component Statistics
---------------------------------------------------------------------------------
Hierarchical RTL Component report
Module t_date
Detailed RTL Component Info :
+---Registers :
8 Bit Registers := 3
+---Muxes :
2 Input 8 Bit Muxes := 6
7 Input 8 Bit Muxes := 2
8 Input 8 Bit Muxes := 6
9 Input 8 Bit Muxes := 2
3 Input 8 Bit Muxes := 1
4 Input 8 Bit Muxes := 1
5 Input 8 Bit Muxes := 1
6 Input 8 Bit Muxes := 1
8 Input 3 Bit Muxes := 1
2 Input 1 Bit Muxes := 9
6 Input 1 Bit Muxes := 2
7 Input 1 Bit Muxes := 2
8 Input 1 Bit Muxes := 4
9 Input 1 Bit Muxes := 2
3 Input 1 Bit Muxes := 1
4 Input 1 Bit Muxes := 1
5 Input 1 Bit Muxes := 1
Module clk
Detailed RTL Component Info :
+---Adders :
2 Input 26 Bit Adders := 1
2 Input 12 Bit Adders := 1
+---Registers :
26 Bit Registers := 1
12 Bit Registers := 1
1 Bit Registers := 2
+---Muxes :
2 Input 26 Bit Muxes := 1
2 Input 12 Bit Muxes := 1
2 Input 1 Bit Muxes := 2
---------------------------------------------------------------------------------
Finished RTL Hierarchical Component Statistics
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Part Resource Summary
---------------------------------------------------------------------------------
Part Resources:
DSPs: 90 (col length:60)
BRAMs: 100 (col length: RAMB18 60 RAMB36 30)
---------------------------------------------------------------------------------
Finished Part Resource Summary
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Cross Boundary and Area Optimization
---------------------------------------------------------------------------------
Warning: Parallel synthesis criteria is not met
INFO: [Synth 8-5545] ROM "U1/clk_1HZ" won't be mapped to RAM because address size (26) is larger than maximum supported(25)
INFO: [Synth 8-5546] ROM "U1/clk_20kHZ" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "a_h1" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "a_h1" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "a_h2" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "a_h2" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-3886] merging instance 'a_h2_reg[3]' (FDE) to 'a_h2_reg[7]'
INFO: [Synth 8-3886] merging instance 'a_h2_reg[4]' (FDE) to 'a_h2_reg[7]'
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\a_h1_reg[0] )
INFO: [Synth 8-3886] merging instance 'a_h1_reg[3]' (FDE) to 'a_h1_reg[7]'
INFO: [Synth 8-3886] merging instance 'a_h1_reg[4]' (FDE) to 'a_h1_reg[7]'
INFO: [Synth 8-3333] propagating constant 1 across sequential element (\a_h1_reg[6] )
WARNING: [Synth 8-3332] Sequential element (FSM_sequential_state_n_reg[2]) is unused and will be removed from module t_date.
WARNING: [Synth 8-3332] Sequential element (FSM_sequential_state_n_reg[1]) is unused and will be removed from module t_date.
WARNING: [Synth 8-3332] Sequential element (FSM_sequential_state_n_reg[0]) is unused and will be removed from module t_date.
WARNING: [Synth 8-3332] Sequential element (a_h1_reg[6]) is unused and will be removed from module t_date.
WARNING: [Synth 8-3332] Sequential element (a_h1_reg[0]) is unused and will be removed from module t_date.
---------------------------------------------------------------------------------
Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:07 ; elapsed = 00:00:15 . Memory (MB): peak = 788.133 ; gain = 476.559
---------------------------------------------------------------------------------
Report RTL Partitions:
+-+--------------+------------+----------+
| |RTL Partition |Replication |Instances |
+-+--------------+------------+----------+
+-+--------------+------------+----------+
---------------------------------------------------------------------------------
Start Applying XDC Timing Constraints
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:10 ; elapsed = 00:00:22 . Memory (MB): peak = 788.133 ; gain = 476.559
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Timing Optimization
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Timing Optimization : Time (s): cpu = 00:00:10 ; elapsed = 00:00:22 . Memory (MB): peak = 788.133 ; gain = 476.559
---------------------------------------------------------------------------------
Report RTL Partitions:
+-+--------------+------------+----------+
| |RTL Partition |Replication |Instances |
+-+--------------+------------+----------+
+-+--------------+------------+----------+
---------------------------------------------------------------------------------
Start Technology Mapping
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Technology Mapping : Time (s): cpu = 00:00:10 ; elapsed = 00:00:22 . Memory (MB): peak = 807.078 ; gain = 495.504
---------------------------------------------------------------------------------
Report RTL Partitions:
+-+--------------+------------+----------+
| |RTL Partition |Replication |Instances |
+-+--------------+------------+----------+
+-+--------------+------------+----------+
---------------------------------------------------------------------------------
Start IO Insertion
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Flattening Before IO Insertion
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Flattening Before IO Insertion
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Final Netlist Cleanup
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Final Netlist Cleanup
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished IO Insertion : Time (s): cpu = 00:00:11 ; elapsed = 00:00:23 . Memory (MB): peak = 807.078 ; gain = 495.504
---------------------------------------------------------------------------------
Report Check Netlist:
+------+------------------+-------+---------+-------+------------------+
| |Item |Errors |Warnings |Status |Description |
+------+------------------+-------+---------+-------+------------------+
|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets |
+------+------------------+-------+---------+-------+------------------+
---------------------------------------------------------------------------------
Start Renaming Generated Instances
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Instances : Time (s): cpu = 00:00:11 ; elapsed = 00:00:23 . Memory (MB): peak = 807.078 ; gain = 495.504
---------------------------------------------------------------------------------
Report RTL Partitions:
+-+--------------+------------+----------+
| |RTL Partition |Replication |Instances |
+-+--------------+------------+----------+
+-+--------------+------------+----------+
---------------------------------------------------------------------------------
Start Rebuilding User Hierarchy
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:11 ; elapsed = 00:00:23 . Memory (MB): peak = 807.078 ; gain = 495.504
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Ports
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Ports : Time (s): cpu = 00:00:11 ; elapsed = 00:00:23 . Memory (MB): peak = 807.078 ; gain = 495.504
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Handling Custom Attributes
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Handling Custom Attributes : Time (s): cpu = 00:00:11 ; elapsed = 00:00:23 . Memory (MB): peak = 807.078 ; gain = 495.504
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Nets
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Nets : Time (s): cpu = 00:00:11 ; elapsed = 00:00:23 . Memory (MB): peak = 807.078 ; gain = 495.504
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Writing Synthesis Report
---------------------------------------------------------------------------------
Report BlackBoxes:
+-+--------------+----------+
| |BlackBox name |Instances |
+-+--------------+----------+
+-+--------------+----------+
Report Cell Usage:
+------+-------+------+
| |Cell |Count |
+------+-------+------+
|1 |BUFG | 1|
|2 |CARRY4 | 10|
|3 |LUT1 | 3|
|4 |LUT2 | 41|
|5 |LUT3 | 5|
|6 |LUT4 | 9|
|7 |LUT5 | 7|
|8 |LUT6 | 18|
|9 |FDCE | 43|
|10 |FDRE | 17|
|11 |FDSE | 1|
|12 |IBUF | 2|
|13 |OBUF | 24|
+------+-------+------+
Report Instance Areas:
+------+---------+-------+------+
| |Instance |Module |Cells |
+------+---------+-------+------+
|1 |top | | 181|
|2 | U1 |clk | 100|
+------+---------+-------+------+
---------------------------------------------------------------------------------
Finished Writing Synthesis Report : Time (s): cpu = 00:00:11 ; elapsed = 00:00:23 . Memory (MB): peak = 807.078 ; gain = 495.504
---------------------------------------------------------------------------------
Synthesis finished with 0 errors, 0 critical warnings and 8 warnings.
Synthesis Optimization Runtime : Time (s): cpu = 00:00:06 ; elapsed = 00:00:17 . Memory (MB): peak = 807.078 ; gain = 170.832
Synthesis Optimization Complete : Time (s): cpu = 00:00:11 ; elapsed = 00:00:23 . Memory (MB): peak = 807.078 ; gain = 495.504
INFO: [Project 1-571] Translating synthesized netlist
INFO: [Netlist 29-17] Analyzing 12 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
INFO: [Project 1-570] Preparing netlist for logic optimization
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
INFO: [Project 1-111] Unisim Transformation Summary:
No Unisim elements were transformed.
INFO: [Common 17-83] Releasing license: Synthesis
54 Infos, 8 Warnings, 0 Critical Warnings and 0 Errors encountered.
synth_design completed successfully
synth_design: Time (s): cpu = 00:00:12 ; elapsed = 00:00:25 . Memory (MB): peak = 807.078 ; gain = 508.328
INFO: [Common 17-1381] The checkpoint 'Z:/Storage/Schoolwork/DigitalLogic/test/test.runs/synth_1/t_date.dcp' has been generated.
INFO: [runtcl-4] Executing : report_utilization -file t_date_utilization_synth.rpt -pb t_date_utilization_synth.pb
report_utilization: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.012 . Memory (MB): peak = 807.078 ; gain = 0.000
INFO: [Common 17-206] Exiting Vivado at Thu Dec 19 03:42:49 2024...

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Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
-------------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2018.1 (win64) Build 2188600 Wed Apr 4 18:40:38 MDT 2018
| Date : Thu Dec 19 03:42:49 2024
| Host : WIN-P8FUKGQFPK3 running 64-bit major release (build 9200)
| Command : report_utilization -file t_date_utilization_synth.rpt -pb t_date_utilization_synth.pb
| Design : t_date
| Device : 7a35tcsg324-1
| Design State : Synthesized
-------------------------------------------------------------------------------------------------------
Utilization Design Information
Table of Contents
-----------------
1. Slice Logic
1.1 Summary of Registers by Type
2. Memory
3. DSP
4. IO and GT Specific
5. Clocking
6. Specific Feature
7. Primitives
8. Black Boxes
9. Instantiated Netlists
1. Slice Logic
--------------
+-------------------------+------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+-------------------------+------+-------+-----------+-------+
| Slice LUTs* | 63 | 0 | 20800 | 0.30 |
| LUT as Logic | 63 | 0 | 20800 | 0.30 |
| LUT as Memory | 0 | 0 | 9600 | 0.00 |
| Slice Registers | 61 | 0 | 41600 | 0.15 |
| Register as Flip Flop | 61 | 0 | 41600 | 0.15 |
| Register as Latch | 0 | 0 | 41600 | 0.00 |
| F7 Muxes | 0 | 0 | 16300 | 0.00 |
| F8 Muxes | 0 | 0 | 8150 | 0.00 |
+-------------------------+------+-------+-----------+-------+
* Warning! The Final LUT count, after physical optimizations and full implementation, is typically lower. Run opt_design after synthesis, if not already completed, for a more realistic count.
1.1 Summary of Registers by Type
--------------------------------
+-------+--------------+-------------+--------------+
| Total | Clock Enable | Synchronous | Asynchronous |
+-------+--------------+-------------+--------------+
| 0 | _ | - | - |
| 0 | _ | - | Set |
| 0 | _ | - | Reset |
| 0 | _ | Set | - |
| 0 | _ | Reset | - |
| 0 | Yes | - | - |
| 0 | Yes | - | Set |
| 43 | Yes | - | Reset |
| 1 | Yes | Set | - |
| 17 | Yes | Reset | - |
+-------+--------------+-------------+--------------+
2. Memory
---------
+----------------+------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+----------------+------+-------+-----------+-------+
| Block RAM Tile | 0 | 0 | 50 | 0.00 |
| RAMB36/FIFO* | 0 | 0 | 50 | 0.00 |
| RAMB18 | 0 | 0 | 100 | 0.00 |
+----------------+------+-------+-----------+-------+
* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1
3. DSP
------
+-----------+------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+-----------+------+-------+-----------+-------+
| DSPs | 0 | 0 | 90 | 0.00 |
+-----------+------+-------+-----------+-------+
4. IO and GT Specific
---------------------
+-----------------------------+------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+-----------------------------+------+-------+-----------+-------+
| Bonded IOB | 26 | 0 | 210 | 12.38 |
| Bonded IPADs | 0 | 0 | 2 | 0.00 |
| PHY_CONTROL | 0 | 0 | 5 | 0.00 |
| PHASER_REF | 0 | 0 | 5 | 0.00 |
| OUT_FIFO | 0 | 0 | 20 | 0.00 |
| IN_FIFO | 0 | 0 | 20 | 0.00 |
| IDELAYCTRL | 0 | 0 | 5 | 0.00 |
| IBUFDS | 0 | 0 | 202 | 0.00 |
| PHASER_OUT/PHASER_OUT_PHY | 0 | 0 | 20 | 0.00 |
| PHASER_IN/PHASER_IN_PHY | 0 | 0 | 20 | 0.00 |
| IDELAYE2/IDELAYE2_FINEDELAY | 0 | 0 | 250 | 0.00 |
| ILOGIC | 0 | 0 | 210 | 0.00 |
| OLOGIC | 0 | 0 | 210 | 0.00 |
+-----------------------------+------+-------+-----------+-------+
5. Clocking
-----------
+------------+------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+------------+------+-------+-----------+-------+
| BUFGCTRL | 1 | 0 | 32 | 3.13 |
| BUFIO | 0 | 0 | 20 | 0.00 |
| MMCME2_ADV | 0 | 0 | 5 | 0.00 |
| PLLE2_ADV | 0 | 0 | 5 | 0.00 |
| BUFMRCE | 0 | 0 | 10 | 0.00 |
| BUFHCE | 0 | 0 | 72 | 0.00 |
| BUFR | 0 | 0 | 20 | 0.00 |
+------------+------+-------+-----------+-------+
6. Specific Feature
-------------------
+-------------+------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+-------------+------+-------+-----------+-------+
| BSCANE2 | 0 | 0 | 4 | 0.00 |
| CAPTUREE2 | 0 | 0 | 1 | 0.00 |
| DNA_PORT | 0 | 0 | 1 | 0.00 |
| EFUSE_USR | 0 | 0 | 1 | 0.00 |
| FRAME_ECCE2 | 0 | 0 | 1 | 0.00 |
| ICAPE2 | 0 | 0 | 2 | 0.00 |
| PCIE_2_1 | 0 | 0 | 1 | 0.00 |
| STARTUPE2 | 0 | 0 | 1 | 0.00 |
| XADC | 0 | 0 | 1 | 0.00 |
+-------------+------+-------+-----------+-------+
7. Primitives
-------------
+----------+------+---------------------+
| Ref Name | Used | Functional Category |
+----------+------+---------------------+
| FDCE | 43 | Flop & Latch |
| LUT2 | 41 | LUT |
| OBUF | 24 | IO |
| LUT6 | 18 | LUT |
| FDRE | 17 | Flop & Latch |
| CARRY4 | 10 | CarryLogic |
| LUT4 | 9 | LUT |
| LUT5 | 7 | LUT |
| LUT3 | 5 | LUT |
| LUT1 | 3 | LUT |
| IBUF | 2 | IO |
| FDSE | 1 | Flop & Latch |
| BUFG | 1 | Clock |
+----------+------+---------------------+
8. Black Boxes
--------------
+----------+------+
| Ref Name | Used |
+----------+------+
9. Instantiated Netlists
------------------------
+----------+------+
| Ref Name | Used |
+----------+------+

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#-----------------------------------------------------------
# Vivado v2018.1 (64-bit)
# SW Build 2188600 on Wed Apr 4 18:40:38 MDT 2018
# IP Build 2185939 on Wed Apr 4 20:55:05 MDT 2018
# Start of session at: Thu Dec 19 03:42:19 2024
# Process ID: 3132
# Current directory: Z:/Storage/Schoolwork/DigitalLogic/test/test.runs/synth_1
# Command line: vivado.exe -log t_date.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source t_date.tcl
# Log file: Z:/Storage/Schoolwork/DigitalLogic/test/test.runs/synth_1/t_date.vds
# Journal file: Z:/Storage/Schoolwork/DigitalLogic/test/test.runs/synth_1\vivado.jou
#-----------------------------------------------------------
source t_date.tcl -notrace

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