Initial commit
This commit is contained in:
53
test/test.runs/synth_1/.Xil/t_date_propImpl.xdc
Normal file
53
test/test.runs/synth_1/.Xil/t_date_propImpl.xdc
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@@ -0,0 +1,53 @@
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||||
set_property SRC_FILE_INFO {cfile:Z:/Storage/Schoolwork/DigitalLogic/test/test.srcs/constrs_1/imports/Downloads/EX1.xdc rfile:../../../test.srcs/constrs_1/imports/Downloads/EX1.xdc id:1} [current_design]
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set_property src_info {type:XDC file:1 line:27 export:INPUT save:INPUT read:READ} [current_design]
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set_property PACKAGE_PIN P17 [get_ports clk]
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set_property src_info {type:XDC file:1 line:28 export:INPUT save:INPUT read:READ} [current_design]
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set_property PACKAGE_PIN R15 [get_ports rst]
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set_property src_info {type:XDC file:1 line:29 export:INPUT save:INPUT read:READ} [current_design]
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set_property PACKAGE_PIN B4 [get_ports {a_h1[7]}]
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set_property src_info {type:XDC file:1 line:30 export:INPUT save:INPUT read:READ} [current_design]
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set_property PACKAGE_PIN A4 [get_ports {a_h1[6]}]
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set_property src_info {type:XDC file:1 line:31 export:INPUT save:INPUT read:READ} [current_design]
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set_property PACKAGE_PIN A3 [get_ports {a_h1[5]}]
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set_property src_info {type:XDC file:1 line:32 export:INPUT save:INPUT read:READ} [current_design]
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set_property PACKAGE_PIN B1 [get_ports {a_h1[4]}]
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set_property src_info {type:XDC file:1 line:33 export:INPUT save:INPUT read:READ} [current_design]
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set_property PACKAGE_PIN A1 [get_ports {a_h1[3]}]
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set_property src_info {type:XDC file:1 line:34 export:INPUT save:INPUT read:READ} [current_design]
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set_property PACKAGE_PIN B3 [get_ports {a_h1[2]}]
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set_property src_info {type:XDC file:1 line:35 export:INPUT save:INPUT read:READ} [current_design]
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set_property PACKAGE_PIN B2 [get_ports {a_h1[1]}]
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set_property src_info {type:XDC file:1 line:36 export:INPUT save:INPUT read:READ} [current_design]
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set_property PACKAGE_PIN D5 [get_ports {a_h1[0]}]
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set_property src_info {type:XDC file:1 line:37 export:INPUT save:INPUT read:READ} [current_design]
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set_property PACKAGE_PIN D4 [get_ports {a_h2[7]}]
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set_property src_info {type:XDC file:1 line:38 export:INPUT save:INPUT read:READ} [current_design]
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set_property PACKAGE_PIN E3 [get_ports {a_h2[6]}]
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set_property src_info {type:XDC file:1 line:39 export:INPUT save:INPUT read:READ} [current_design]
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set_property PACKAGE_PIN D3 [get_ports {a_h2[5]}]
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set_property src_info {type:XDC file:1 line:40 export:INPUT save:INPUT read:READ} [current_design]
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set_property PACKAGE_PIN F4 [get_ports {a_h2[4]}]
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set_property src_info {type:XDC file:1 line:41 export:INPUT save:INPUT read:READ} [current_design]
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set_property PACKAGE_PIN F3 [get_ports {a_h2[3]}]
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set_property src_info {type:XDC file:1 line:42 export:INPUT save:INPUT read:READ} [current_design]
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set_property PACKAGE_PIN E2 [get_ports {a_h2[2]}]
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set_property src_info {type:XDC file:1 line:43 export:INPUT save:INPUT read:READ} [current_design]
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set_property PACKAGE_PIN D2 [get_ports {a_h2[1]}]
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set_property src_info {type:XDC file:1 line:44 export:INPUT save:INPUT read:READ} [current_design]
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set_property PACKAGE_PIN H2 [get_ports {a_h2[0]}]
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set_property src_info {type:XDC file:1 line:45 export:INPUT save:INPUT read:READ} [current_design]
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set_property PACKAGE_PIN G2 [get_ports {an[7]}]
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set_property src_info {type:XDC file:1 line:46 export:INPUT save:INPUT read:READ} [current_design]
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set_property PACKAGE_PIN C2 [get_ports {an[6]}]
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set_property src_info {type:XDC file:1 line:47 export:INPUT save:INPUT read:READ} [current_design]
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set_property PACKAGE_PIN C1 [get_ports {an[5]}]
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set_property src_info {type:XDC file:1 line:48 export:INPUT save:INPUT read:READ} [current_design]
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set_property PACKAGE_PIN H1 [get_ports {an[4]}]
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set_property src_info {type:XDC file:1 line:49 export:INPUT save:INPUT read:READ} [current_design]
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set_property PACKAGE_PIN G1 [get_ports {an[3]}]
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set_property src_info {type:XDC file:1 line:50 export:INPUT save:INPUT read:READ} [current_design]
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set_property PACKAGE_PIN F1 [get_ports {an[2]}]
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set_property src_info {type:XDC file:1 line:51 export:INPUT save:INPUT read:READ} [current_design]
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set_property PACKAGE_PIN E1 [get_ports {an[1]}]
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set_property src_info {type:XDC file:1 line:52 export:INPUT save:INPUT read:READ} [current_design]
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set_property PACKAGE_PIN G6 [get_ports {an[0]}]
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66
test/test.runs/synth_1/gen_run.xml
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66
test/test.runs/synth_1/gen_run.xml
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@@ -0,0 +1,66 @@
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<?xml version="1.0" encoding="UTF-8"?>
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<GenRun Id="synth_1" LaunchPart="xc7a35tcsg324-1" LaunchTime="1734550937">
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<File Type="PA-TCL" Name="t_date.tcl"/>
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<File Type="RDS-PROPCONSTRS" Name="t_date_drc_synth.rpt"/>
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<File Type="REPORTS-TCL" Name="t_date_reports.tcl"/>
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<File Type="RDS-RDS" Name="t_date.vds"/>
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<File Type="RDS-UTIL" Name="t_date_utilization_synth.rpt"/>
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<File Type="RDS-UTIL-PB" Name="t_date_utilization_synth.pb"/>
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<File Type="RDS-DCP" Name="t_date.dcp"/>
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<File Type="VDS-TIMINGSUMMARY" Name="t_date_timing_summary_synth.rpt"/>
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<File Type="VDS-TIMING-PB" Name="t_date_timing_summary_synth.pb"/>
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<FileSet Name="sources" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1">
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<Filter Type="Srcs"/>
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<File Path="$PSRCDIR/sources_1/imports/Downloads/slow.v">
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<FileInfo>
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<Attr Name="ImportPath" Val="$PPRDIR/../../../Downloads/slow.v"/>
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<Attr Name="ImportTime" Val="1734532876"/>
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<Attr Name="UsedIn" Val="synthesis"/>
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<Attr Name="UsedIn" Val="implementation"/>
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<Attr Name="UsedIn" Val="simulation"/>
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</FileInfo>
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</File>
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<File Path="$PSRCDIR/sources_1/imports/Downloads/t_date.v">
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<FileInfo>
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<Attr Name="ImportPath" Val="$PPRDIR/../../../Downloads/t_date.v"/>
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<Attr Name="ImportTime" Val="1734443575"/>
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<Attr Name="UsedIn" Val="synthesis"/>
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<Attr Name="UsedIn" Val="implementation"/>
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<Attr Name="UsedIn" Val="simulation"/>
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</FileInfo>
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</File>
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<File Path="$PSRCDIR/sources_1/imports/Downloads/OUT.v">
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<FileInfo>
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<Attr Name="AutoDisabled" Val="1"/>
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<Attr Name="ImportPath" Val="$PPRDIR/../../../Downloads/OUT.v"/>
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<Attr Name="ImportTime" Val="1734532870"/>
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<Attr Name="UsedIn" Val="synthesis"/>
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<Attr Name="UsedIn" Val="implementation"/>
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<Attr Name="UsedIn" Val="simulation"/>
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</FileInfo>
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</File>
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<Config>
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<Option Name="DesignMode" Val="RTL"/>
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<Option Name="TopModule" Val="t_date"/>
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<Option Name="TopAutoSet" Val="TRUE"/>
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</Config>
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</FileSet>
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<FileSet Name="constrs_in" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1">
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<Filter Type="Constrs"/>
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<File Path="$PSRCDIR/constrs_1/imports/Downloads/EX1.xdc">
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<FileInfo>
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<Attr Name="ImportPath" Val="$PPRDIR/../../../Downloads/EX1.xdc"/>
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<Attr Name="ImportTime" Val="1734529765"/>
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<Attr Name="UsedIn" Val="synthesis"/>
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<Attr Name="UsedIn" Val="implementation"/>
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</FileInfo>
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</File>
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<Config>
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<Option Name="ConstrsType" Val="XDC"/>
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</Config>
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</FileSet>
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<Strategy Version="1" Minor="2">
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<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2018"/>
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<Step Id="synth_design"/>
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</Strategy>
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</GenRun>
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9
test/test.runs/synth_1/htr.txt
Normal file
9
test/test.runs/synth_1/htr.txt
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@@ -0,0 +1,9 @@
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REM
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REM Vivado(TM)
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REM htr.txt: a Vivado-generated description of how-to-repeat the
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REM the basic steps of a run. Note that runme.bat/sh needs
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REM to be invoked for Vivado to track run status.
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REM Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
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REM
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vivado -log t_date.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source t_date.tcl
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BIN
test/test.runs/synth_1/t_date.dcp
Normal file
BIN
test/test.runs/synth_1/t_date.dcp
Normal file
Binary file not shown.
57
test/test.runs/synth_1/t_date.tcl
Normal file
57
test/test.runs/synth_1/t_date.tcl
Normal file
@@ -0,0 +1,57 @@
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#
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# Synthesis run script generated by Vivado
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#
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proc create_report { reportName command } {
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set status "."
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append status $reportName ".fail"
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if { [file exists $status] } {
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eval file delete [glob $status]
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}
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send_msg_id runtcl-4 info "Executing : $command"
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set retval [eval catch { $command } msg]
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if { $retval != 0 } {
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set fp [open $status w]
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close $fp
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send_msg_id runtcl-5 warning "$msg"
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}
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}
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set_param xicom.use_bs_reader 1
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create_project -in_memory -part xc7a35tcsg324-1
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set_param project.singleFileAddWarning.threshold 0
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set_param project.compositeFile.enableAutoGeneration 0
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set_param synth.vivado.isSynthRun true
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set_property webtalk.parent_dir Z:/Storage/Schoolwork/DigitalLogic/test/test.cache/wt [current_project]
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set_property parent.project_path Z:/Storage/Schoolwork/DigitalLogic/test/test.xpr [current_project]
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set_property default_lib xil_defaultlib [current_project]
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set_property target_language Verilog [current_project]
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set_property ip_output_repo z:/Storage/Schoolwork/DigitalLogic/test/test.cache/ip [current_project]
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set_property ip_cache_permissions {read write} [current_project]
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read_verilog -library xil_defaultlib {
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Z:/Storage/Schoolwork/DigitalLogic/test/test.srcs/sources_1/imports/Downloads/slow.v
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Z:/Storage/Schoolwork/DigitalLogic/test/test.srcs/sources_1/imports/Downloads/t_date.v
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}
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# Mark all dcp files as not used in implementation to prevent them from being
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# stitched into the results of this synthesis run. Any black boxes in the
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# design are intentionally left as such for best results. Dcp files will be
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# stitched into the design at a later time, either when this synthesis run is
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# opened, or when it is stitched into a dependent implementation run.
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foreach dcp [get_files -quiet -all -filter file_type=="Design\ Checkpoint"] {
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set_property used_in_implementation false $dcp
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}
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read_xdc Z:/Storage/Schoolwork/DigitalLogic/test/test.srcs/constrs_1/imports/Downloads/EX1.xdc
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set_property used_in_implementation false [get_files Z:/Storage/Schoolwork/DigitalLogic/test/test.srcs/constrs_1/imports/Downloads/EX1.xdc]
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set_param ips.enableIPCacheLiteLoad 0
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close [open __synthesis_is_running__ w]
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synth_design -top t_date -part xc7a35tcsg324-1
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|
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# disable binary constraint mode for synth run checkpoints
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set_param constraints.enableBinaryConstraints false
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write_checkpoint -force -noxdef t_date.dcp
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create_report "synth_1_synth_report_utilization_0" "report_utilization -file t_date_utilization_synth.rpt -pb t_date_utilization_synth.pb"
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file delete __synthesis_is_running__
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close [open __synthesis_is_complete__ w]
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403
test/test.runs/synth_1/t_date.vds
Normal file
403
test/test.runs/synth_1/t_date.vds
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@@ -0,0 +1,403 @@
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#-----------------------------------------------------------
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# Vivado v2018.1 (64-bit)
|
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# SW Build 2188600 on Wed Apr 4 18:40:38 MDT 2018
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# IP Build 2185939 on Wed Apr 4 20:55:05 MDT 2018
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# Start of session at: Thu Dec 19 03:42:19 2024
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# Process ID: 3132
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# Current directory: Z:/Storage/Schoolwork/DigitalLogic/test/test.runs/synth_1
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# Command line: vivado.exe -log t_date.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source t_date.tcl
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# Log file: Z:/Storage/Schoolwork/DigitalLogic/test/test.runs/synth_1/t_date.vds
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# Journal file: Z:/Storage/Schoolwork/DigitalLogic/test/test.runs/synth_1\vivado.jou
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#-----------------------------------------------------------
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source t_date.tcl -notrace
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Command: synth_design -top t_date -part xc7a35tcsg324-1
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Starting synth_design
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Attempting to get a license for feature 'Synthesis' and/or device 'xc7a35t'
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INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7a35t'
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||||
INFO: Launching helper process for spawning children vivado processes
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INFO: Helper process launched with PID 692
|
||||
---------------------------------------------------------------------------------
|
||||
Starting RTL Elaboration : Time (s): cpu = 00:00:02 ; elapsed = 00:00:04 . Memory (MB): peak = 407.832 ; gain = 96.258
|
||||
---------------------------------------------------------------------------------
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||||
INFO: [Synth 8-6157] synthesizing module 't_date' [Z:/Storage/Schoolwork/DigitalLogic/test/test.srcs/sources_1/imports/Downloads/t_date.v:23]
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Parameter y0 bound to: 4'b0000
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||||
Parameter y1 bound to: 4'b0001
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||||
Parameter y2 bound to: 4'b0010
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||||
Parameter y3 bound to: 4'b0011
|
||||
Parameter y4 bound to: 4'b0100
|
||||
Parameter y5 bound to: 4'b0101
|
||||
Parameter y6 bound to: 4'b0110
|
||||
Parameter y7 bound to: 4'b0111
|
||||
INFO: [Synth 8-6157] synthesizing module 'clk' [Z:/Storage/Schoolwork/DigitalLogic/test/test.srcs/sources_1/imports/Downloads/slow.v:23]
|
||||
Parameter sys_clk bound to: 100000000 - type: integer
|
||||
Parameter clk_out1 bound to: 1 - type: integer
|
||||
Parameter clk_out20k bound to: 20000 - type: integer
|
||||
Parameter max1 bound to: 49999999 - type: integer
|
||||
Parameter max20k bound to: 2499 - type: integer
|
||||
INFO: [Synth 8-6155] done synthesizing module 'clk' (1#1) [Z:/Storage/Schoolwork/DigitalLogic/test/test.srcs/sources_1/imports/Downloads/slow.v:23]
|
||||
INFO: [Synth 8-155] case statement is not full and has no default [Z:/Storage/Schoolwork/DigitalLogic/test/test.srcs/sources_1/imports/Downloads/t_date.v:38]
|
||||
INFO: [Synth 8-155] case statement is not full and has no default [Z:/Storage/Schoolwork/DigitalLogic/test/test.srcs/sources_1/imports/Downloads/t_date.v:57]
|
||||
INFO: [Synth 8-155] case statement is not full and has no default [Z:/Storage/Schoolwork/DigitalLogic/test/test.srcs/sources_1/imports/Downloads/t_date.v:63]
|
||||
INFO: [Synth 8-155] case statement is not full and has no default [Z:/Storage/Schoolwork/DigitalLogic/test/test.srcs/sources_1/imports/Downloads/t_date.v:70]
|
||||
INFO: [Synth 8-155] case statement is not full and has no default [Z:/Storage/Schoolwork/DigitalLogic/test/test.srcs/sources_1/imports/Downloads/t_date.v:78]
|
||||
INFO: [Synth 8-155] case statement is not full and has no default [Z:/Storage/Schoolwork/DigitalLogic/test/test.srcs/sources_1/imports/Downloads/t_date.v:87]
|
||||
INFO: [Synth 8-155] case statement is not full and has no default [Z:/Storage/Schoolwork/DigitalLogic/test/test.srcs/sources_1/imports/Downloads/t_date.v:97]
|
||||
INFO: [Synth 8-155] case statement is not full and has no default [Z:/Storage/Schoolwork/DigitalLogic/test/test.srcs/sources_1/imports/Downloads/t_date.v:108]
|
||||
INFO: [Synth 8-155] case statement is not full and has no default [Z:/Storage/Schoolwork/DigitalLogic/test/test.srcs/sources_1/imports/Downloads/t_date.v:52]
|
||||
INFO: [Synth 8-6155] done synthesizing module 't_date' (2#1) [Z:/Storage/Schoolwork/DigitalLogic/test/test.srcs/sources_1/imports/Downloads/t_date.v:23]
|
||||
---------------------------------------------------------------------------------
|
||||
Finished RTL Elaboration : Time (s): cpu = 00:00:03 ; elapsed = 00:00:04 . Memory (MB): peak = 463.461 ; gain = 151.887
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Report Check Netlist:
|
||||
+------+------------------+-------+---------+-------+------------------+
|
||||
| |Item |Errors |Warnings |Status |Description |
|
||||
+------+------------------+-------+---------+-------+------------------+
|
||||
|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets |
|
||||
+------+------------------+-------+---------+-------+------------------+
|
||||
---------------------------------------------------------------------------------
|
||||
Start Handling Custom Attributes
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Handling Custom Attributes : Time (s): cpu = 00:00:03 ; elapsed = 00:00:05 . Memory (MB): peak = 463.461 ; gain = 151.887
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:03 ; elapsed = 00:00:05 . Memory (MB): peak = 463.461 ; gain = 151.887
|
||||
---------------------------------------------------------------------------------
|
||||
INFO: [Device 21-403] Loading part xc7a35tcsg324-1
|
||||
INFO: [Project 1-570] Preparing netlist for logic optimization
|
||||
|
||||
Processing XDC Constraints
|
||||
Initializing timing engine
|
||||
Parsing XDC File [Z:/Storage/Schoolwork/DigitalLogic/test/test.srcs/constrs_1/imports/Downloads/EX1.xdc]
|
||||
Finished Parsing XDC File [Z:/Storage/Schoolwork/DigitalLogic/test/test.srcs/constrs_1/imports/Downloads/EX1.xdc]
|
||||
INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [Z:/Storage/Schoolwork/DigitalLogic/test/test.srcs/constrs_1/imports/Downloads/EX1.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/t_date_propImpl.xdc].
|
||||
Resolution: To avoid this warning, move constraints listed in [.Xil/t_date_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
|
||||
Completed Processing XDC Constraints
|
||||
|
||||
INFO: [Project 1-111] Unisim Transformation Summary:
|
||||
No Unisim elements were transformed.
|
||||
|
||||
Constraint Validation Runtime : Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.004 . Memory (MB): peak = 788.133 ; gain = 0.000
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Constraint Validation : Time (s): cpu = 00:00:07 ; elapsed = 00:00:14 . Memory (MB): peak = 788.133 ; gain = 476.559
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Loading Part and Timing Information
|
||||
---------------------------------------------------------------------------------
|
||||
Loading part: xc7a35tcsg324-1
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Loading Part and Timing Information : Time (s): cpu = 00:00:07 ; elapsed = 00:00:14 . Memory (MB): peak = 788.133 ; gain = 476.559
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Applying 'set_property' XDC Constraints
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:07 ; elapsed = 00:00:14 . Memory (MB): peak = 788.133 ; gain = 476.559
|
||||
---------------------------------------------------------------------------------
|
||||
INFO: [Synth 8-5545] ROM "clk_1HZ" won't be mapped to RAM because address size (26) is larger than maximum supported(25)
|
||||
INFO: [Synth 8-5546] ROM "clk_20kHZ" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-802] inferred FSM for state register 'state_c_reg' in module 't_date'
|
||||
INFO: [Synth 8-5546] ROM "a_h2" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "a_h2" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "a_h2" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "a_h2" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "a_h2" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "a_h2" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "a_h2" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "a_h1" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "a_h1" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "a_h1" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "a_h1" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5544] ROM "an" won't be mapped to Block RAM because address size (4) smaller than threshold (5)
|
||||
INFO: [Synth 8-5544] ROM "state_n" won't be mapped to Block RAM because address size (4) smaller than threshold (5)
|
||||
WARNING: [Synth 8-327] inferring latch for variable 'FSM_sequential_state_n_reg' [Z:/Storage/Schoolwork/DigitalLogic/test/test.srcs/sources_1/imports/Downloads/t_date.v:39]
|
||||
WARNING: [Synth 8-327] inferring latch for variable 'FSM_onehot_state_n_reg' [Z:/Storage/Schoolwork/DigitalLogic/test/test.srcs/sources_1/imports/Downloads/t_date.v:39]
|
||||
---------------------------------------------------------------------------------------------------
|
||||
State | New Encoding | Previous Encoding
|
||||
---------------------------------------------------------------------------------------------------
|
||||
iSTATE | 000 | 0000
|
||||
iSTATE0 | 001 | 0001
|
||||
iSTATE1 | 010 | 0010
|
||||
iSTATE2 | 011 | 0011
|
||||
iSTATE3 | 100 | 0100
|
||||
iSTATE4 | 101 | 0101
|
||||
iSTATE5 | 110 | 0110
|
||||
iSTATE6 | 111 | 0111
|
||||
---------------------------------------------------------------------------------------------------
|
||||
INFO: [Synth 8-3354] encoded FSM with state register 'state_c_reg' using encoding 'sequential' in module 't_date'
|
||||
WARNING: [Synth 8-327] inferring latch for variable 'FSM_sequential_state_n_reg' [Z:/Storage/Schoolwork/DigitalLogic/test/test.srcs/sources_1/imports/Downloads/t_date.v:39]
|
||||
---------------------------------------------------------------------------------
|
||||
Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:07 ; elapsed = 00:00:14 . Memory (MB): peak = 788.133 ; gain = 476.559
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Report RTL Partitions:
|
||||
+-+--------------+------------+----------+
|
||||
| |RTL Partition |Replication |Instances |
|
||||
+-+--------------+------------+----------+
|
||||
+-+--------------+------------+----------+
|
||||
---------------------------------------------------------------------------------
|
||||
Start RTL Component Statistics
|
||||
---------------------------------------------------------------------------------
|
||||
Detailed RTL Component Info :
|
||||
+---Adders :
|
||||
2 Input 26 Bit Adders := 1
|
||||
2 Input 12 Bit Adders := 1
|
||||
+---Registers :
|
||||
26 Bit Registers := 1
|
||||
12 Bit Registers := 1
|
||||
8 Bit Registers := 3
|
||||
1 Bit Registers := 2
|
||||
+---Muxes :
|
||||
2 Input 26 Bit Muxes := 1
|
||||
2 Input 12 Bit Muxes := 1
|
||||
2 Input 8 Bit Muxes := 6
|
||||
7 Input 8 Bit Muxes := 2
|
||||
8 Input 8 Bit Muxes := 6
|
||||
9 Input 8 Bit Muxes := 2
|
||||
3 Input 8 Bit Muxes := 1
|
||||
4 Input 8 Bit Muxes := 1
|
||||
5 Input 8 Bit Muxes := 1
|
||||
6 Input 8 Bit Muxes := 1
|
||||
8 Input 3 Bit Muxes := 1
|
||||
2 Input 1 Bit Muxes := 11
|
||||
6 Input 1 Bit Muxes := 2
|
||||
7 Input 1 Bit Muxes := 2
|
||||
8 Input 1 Bit Muxes := 4
|
||||
9 Input 1 Bit Muxes := 2
|
||||
3 Input 1 Bit Muxes := 1
|
||||
4 Input 1 Bit Muxes := 1
|
||||
5 Input 1 Bit Muxes := 1
|
||||
---------------------------------------------------------------------------------
|
||||
Finished RTL Component Statistics
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start RTL Hierarchical Component Statistics
|
||||
---------------------------------------------------------------------------------
|
||||
Hierarchical RTL Component report
|
||||
Module t_date
|
||||
Detailed RTL Component Info :
|
||||
+---Registers :
|
||||
8 Bit Registers := 3
|
||||
+---Muxes :
|
||||
2 Input 8 Bit Muxes := 6
|
||||
7 Input 8 Bit Muxes := 2
|
||||
8 Input 8 Bit Muxes := 6
|
||||
9 Input 8 Bit Muxes := 2
|
||||
3 Input 8 Bit Muxes := 1
|
||||
4 Input 8 Bit Muxes := 1
|
||||
5 Input 8 Bit Muxes := 1
|
||||
6 Input 8 Bit Muxes := 1
|
||||
8 Input 3 Bit Muxes := 1
|
||||
2 Input 1 Bit Muxes := 9
|
||||
6 Input 1 Bit Muxes := 2
|
||||
7 Input 1 Bit Muxes := 2
|
||||
8 Input 1 Bit Muxes := 4
|
||||
9 Input 1 Bit Muxes := 2
|
||||
3 Input 1 Bit Muxes := 1
|
||||
4 Input 1 Bit Muxes := 1
|
||||
5 Input 1 Bit Muxes := 1
|
||||
Module clk
|
||||
Detailed RTL Component Info :
|
||||
+---Adders :
|
||||
2 Input 26 Bit Adders := 1
|
||||
2 Input 12 Bit Adders := 1
|
||||
+---Registers :
|
||||
26 Bit Registers := 1
|
||||
12 Bit Registers := 1
|
||||
1 Bit Registers := 2
|
||||
+---Muxes :
|
||||
2 Input 26 Bit Muxes := 1
|
||||
2 Input 12 Bit Muxes := 1
|
||||
2 Input 1 Bit Muxes := 2
|
||||
---------------------------------------------------------------------------------
|
||||
Finished RTL Hierarchical Component Statistics
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Part Resource Summary
|
||||
---------------------------------------------------------------------------------
|
||||
Part Resources:
|
||||
DSPs: 90 (col length:60)
|
||||
BRAMs: 100 (col length: RAMB18 60 RAMB36 30)
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Part Resource Summary
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Cross Boundary and Area Optimization
|
||||
---------------------------------------------------------------------------------
|
||||
Warning: Parallel synthesis criteria is not met
|
||||
INFO: [Synth 8-5545] ROM "U1/clk_1HZ" won't be mapped to RAM because address size (26) is larger than maximum supported(25)
|
||||
INFO: [Synth 8-5546] ROM "U1/clk_20kHZ" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "a_h1" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "a_h1" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "a_h2" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "a_h2" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-3886] merging instance 'a_h2_reg[3]' (FDE) to 'a_h2_reg[7]'
|
||||
INFO: [Synth 8-3886] merging instance 'a_h2_reg[4]' (FDE) to 'a_h2_reg[7]'
|
||||
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\a_h1_reg[0] )
|
||||
INFO: [Synth 8-3886] merging instance 'a_h1_reg[3]' (FDE) to 'a_h1_reg[7]'
|
||||
INFO: [Synth 8-3886] merging instance 'a_h1_reg[4]' (FDE) to 'a_h1_reg[7]'
|
||||
INFO: [Synth 8-3333] propagating constant 1 across sequential element (\a_h1_reg[6] )
|
||||
WARNING: [Synth 8-3332] Sequential element (FSM_sequential_state_n_reg[2]) is unused and will be removed from module t_date.
|
||||
WARNING: [Synth 8-3332] Sequential element (FSM_sequential_state_n_reg[1]) is unused and will be removed from module t_date.
|
||||
WARNING: [Synth 8-3332] Sequential element (FSM_sequential_state_n_reg[0]) is unused and will be removed from module t_date.
|
||||
WARNING: [Synth 8-3332] Sequential element (a_h1_reg[6]) is unused and will be removed from module t_date.
|
||||
WARNING: [Synth 8-3332] Sequential element (a_h1_reg[0]) is unused and will be removed from module t_date.
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:07 ; elapsed = 00:00:15 . Memory (MB): peak = 788.133 ; gain = 476.559
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Report RTL Partitions:
|
||||
+-+--------------+------------+----------+
|
||||
| |RTL Partition |Replication |Instances |
|
||||
+-+--------------+------------+----------+
|
||||
+-+--------------+------------+----------+
|
||||
---------------------------------------------------------------------------------
|
||||
Start Applying XDC Timing Constraints
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:10 ; elapsed = 00:00:22 . Memory (MB): peak = 788.133 ; gain = 476.559
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Timing Optimization
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Timing Optimization : Time (s): cpu = 00:00:10 ; elapsed = 00:00:22 . Memory (MB): peak = 788.133 ; gain = 476.559
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Report RTL Partitions:
|
||||
+-+--------------+------------+----------+
|
||||
| |RTL Partition |Replication |Instances |
|
||||
+-+--------------+------------+----------+
|
||||
+-+--------------+------------+----------+
|
||||
---------------------------------------------------------------------------------
|
||||
Start Technology Mapping
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Technology Mapping : Time (s): cpu = 00:00:10 ; elapsed = 00:00:22 . Memory (MB): peak = 807.078 ; gain = 495.504
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Report RTL Partitions:
|
||||
+-+--------------+------------+----------+
|
||||
| |RTL Partition |Replication |Instances |
|
||||
+-+--------------+------------+----------+
|
||||
+-+--------------+------------+----------+
|
||||
---------------------------------------------------------------------------------
|
||||
Start IO Insertion
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Flattening Before IO Insertion
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Flattening Before IO Insertion
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Final Netlist Cleanup
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Final Netlist Cleanup
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished IO Insertion : Time (s): cpu = 00:00:11 ; elapsed = 00:00:23 . Memory (MB): peak = 807.078 ; gain = 495.504
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Report Check Netlist:
|
||||
+------+------------------+-------+---------+-------+------------------+
|
||||
| |Item |Errors |Warnings |Status |Description |
|
||||
+------+------------------+-------+---------+-------+------------------+
|
||||
|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets |
|
||||
+------+------------------+-------+---------+-------+------------------+
|
||||
---------------------------------------------------------------------------------
|
||||
Start Renaming Generated Instances
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Renaming Generated Instances : Time (s): cpu = 00:00:11 ; elapsed = 00:00:23 . Memory (MB): peak = 807.078 ; gain = 495.504
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Report RTL Partitions:
|
||||
+-+--------------+------------+----------+
|
||||
| |RTL Partition |Replication |Instances |
|
||||
+-+--------------+------------+----------+
|
||||
+-+--------------+------------+----------+
|
||||
---------------------------------------------------------------------------------
|
||||
Start Rebuilding User Hierarchy
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:11 ; elapsed = 00:00:23 . Memory (MB): peak = 807.078 ; gain = 495.504
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Renaming Generated Ports
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Renaming Generated Ports : Time (s): cpu = 00:00:11 ; elapsed = 00:00:23 . Memory (MB): peak = 807.078 ; gain = 495.504
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Handling Custom Attributes
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Handling Custom Attributes : Time (s): cpu = 00:00:11 ; elapsed = 00:00:23 . Memory (MB): peak = 807.078 ; gain = 495.504
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Renaming Generated Nets
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Renaming Generated Nets : Time (s): cpu = 00:00:11 ; elapsed = 00:00:23 . Memory (MB): peak = 807.078 ; gain = 495.504
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Writing Synthesis Report
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Report BlackBoxes:
|
||||
+-+--------------+----------+
|
||||
| |BlackBox name |Instances |
|
||||
+-+--------------+----------+
|
||||
+-+--------------+----------+
|
||||
|
||||
Report Cell Usage:
|
||||
+------+-------+------+
|
||||
| |Cell |Count |
|
||||
+------+-------+------+
|
||||
|1 |BUFG | 1|
|
||||
|2 |CARRY4 | 10|
|
||||
|3 |LUT1 | 3|
|
||||
|4 |LUT2 | 41|
|
||||
|5 |LUT3 | 5|
|
||||
|6 |LUT4 | 9|
|
||||
|7 |LUT5 | 7|
|
||||
|8 |LUT6 | 18|
|
||||
|9 |FDCE | 43|
|
||||
|10 |FDRE | 17|
|
||||
|11 |FDSE | 1|
|
||||
|12 |IBUF | 2|
|
||||
|13 |OBUF | 24|
|
||||
+------+-------+------+
|
||||
|
||||
Report Instance Areas:
|
||||
+------+---------+-------+------+
|
||||
| |Instance |Module |Cells |
|
||||
+------+---------+-------+------+
|
||||
|1 |top | | 181|
|
||||
|2 | U1 |clk | 100|
|
||||
+------+---------+-------+------+
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Writing Synthesis Report : Time (s): cpu = 00:00:11 ; elapsed = 00:00:23 . Memory (MB): peak = 807.078 ; gain = 495.504
|
||||
---------------------------------------------------------------------------------
|
||||
Synthesis finished with 0 errors, 0 critical warnings and 8 warnings.
|
||||
Synthesis Optimization Runtime : Time (s): cpu = 00:00:06 ; elapsed = 00:00:17 . Memory (MB): peak = 807.078 ; gain = 170.832
|
||||
Synthesis Optimization Complete : Time (s): cpu = 00:00:11 ; elapsed = 00:00:23 . Memory (MB): peak = 807.078 ; gain = 495.504
|
||||
INFO: [Project 1-571] Translating synthesized netlist
|
||||
INFO: [Netlist 29-17] Analyzing 12 Unisim elements for replacement
|
||||
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
|
||||
INFO: [Project 1-570] Preparing netlist for logic optimization
|
||||
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
|
||||
INFO: [Project 1-111] Unisim Transformation Summary:
|
||||
No Unisim elements were transformed.
|
||||
|
||||
INFO: [Common 17-83] Releasing license: Synthesis
|
||||
54 Infos, 8 Warnings, 0 Critical Warnings and 0 Errors encountered.
|
||||
synth_design completed successfully
|
||||
synth_design: Time (s): cpu = 00:00:12 ; elapsed = 00:00:25 . Memory (MB): peak = 807.078 ; gain = 508.328
|
||||
INFO: [Common 17-1381] The checkpoint 'Z:/Storage/Schoolwork/DigitalLogic/test/test.runs/synth_1/t_date.dcp' has been generated.
|
||||
INFO: [runtcl-4] Executing : report_utilization -file t_date_utilization_synth.rpt -pb t_date_utilization_synth.pb
|
||||
report_utilization: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.012 . Memory (MB): peak = 807.078 ; gain = 0.000
|
||||
INFO: [Common 17-206] Exiting Vivado at Thu Dec 19 03:42:49 2024...
|
||||
BIN
test/test.runs/synth_1/t_date_utilization_synth.pb
Normal file
BIN
test/test.runs/synth_1/t_date_utilization_synth.pb
Normal file
Binary file not shown.
180
test/test.runs/synth_1/t_date_utilization_synth.rpt
Normal file
180
test/test.runs/synth_1/t_date_utilization_synth.rpt
Normal file
@@ -0,0 +1,180 @@
|
||||
Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
|
||||
-------------------------------------------------------------------------------------------------------
|
||||
| Tool Version : Vivado v.2018.1 (win64) Build 2188600 Wed Apr 4 18:40:38 MDT 2018
|
||||
| Date : Thu Dec 19 03:42:49 2024
|
||||
| Host : WIN-P8FUKGQFPK3 running 64-bit major release (build 9200)
|
||||
| Command : report_utilization -file t_date_utilization_synth.rpt -pb t_date_utilization_synth.pb
|
||||
| Design : t_date
|
||||
| Device : 7a35tcsg324-1
|
||||
| Design State : Synthesized
|
||||
-------------------------------------------------------------------------------------------------------
|
||||
|
||||
Utilization Design Information
|
||||
|
||||
Table of Contents
|
||||
-----------------
|
||||
1. Slice Logic
|
||||
1.1 Summary of Registers by Type
|
||||
2. Memory
|
||||
3. DSP
|
||||
4. IO and GT Specific
|
||||
5. Clocking
|
||||
6. Specific Feature
|
||||
7. Primitives
|
||||
8. Black Boxes
|
||||
9. Instantiated Netlists
|
||||
|
||||
1. Slice Logic
|
||||
--------------
|
||||
|
||||
+-------------------------+------+-------+-----------+-------+
|
||||
| Site Type | Used | Fixed | Available | Util% |
|
||||
+-------------------------+------+-------+-----------+-------+
|
||||
| Slice LUTs* | 63 | 0 | 20800 | 0.30 |
|
||||
| LUT as Logic | 63 | 0 | 20800 | 0.30 |
|
||||
| LUT as Memory | 0 | 0 | 9600 | 0.00 |
|
||||
| Slice Registers | 61 | 0 | 41600 | 0.15 |
|
||||
| Register as Flip Flop | 61 | 0 | 41600 | 0.15 |
|
||||
| Register as Latch | 0 | 0 | 41600 | 0.00 |
|
||||
| F7 Muxes | 0 | 0 | 16300 | 0.00 |
|
||||
| F8 Muxes | 0 | 0 | 8150 | 0.00 |
|
||||
+-------------------------+------+-------+-----------+-------+
|
||||
* Warning! The Final LUT count, after physical optimizations and full implementation, is typically lower. Run opt_design after synthesis, if not already completed, for a more realistic count.
|
||||
|
||||
|
||||
1.1 Summary of Registers by Type
|
||||
--------------------------------
|
||||
|
||||
+-------+--------------+-------------+--------------+
|
||||
| Total | Clock Enable | Synchronous | Asynchronous |
|
||||
+-------+--------------+-------------+--------------+
|
||||
| 0 | _ | - | - |
|
||||
| 0 | _ | - | Set |
|
||||
| 0 | _ | - | Reset |
|
||||
| 0 | _ | Set | - |
|
||||
| 0 | _ | Reset | - |
|
||||
| 0 | Yes | - | - |
|
||||
| 0 | Yes | - | Set |
|
||||
| 43 | Yes | - | Reset |
|
||||
| 1 | Yes | Set | - |
|
||||
| 17 | Yes | Reset | - |
|
||||
+-------+--------------+-------------+--------------+
|
||||
|
||||
|
||||
2. Memory
|
||||
---------
|
||||
|
||||
+----------------+------+-------+-----------+-------+
|
||||
| Site Type | Used | Fixed | Available | Util% |
|
||||
+----------------+------+-------+-----------+-------+
|
||||
| Block RAM Tile | 0 | 0 | 50 | 0.00 |
|
||||
| RAMB36/FIFO* | 0 | 0 | 50 | 0.00 |
|
||||
| RAMB18 | 0 | 0 | 100 | 0.00 |
|
||||
+----------------+------+-------+-----------+-------+
|
||||
* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1
|
||||
|
||||
|
||||
3. DSP
|
||||
------
|
||||
|
||||
+-----------+------+-------+-----------+-------+
|
||||
| Site Type | Used | Fixed | Available | Util% |
|
||||
+-----------+------+-------+-----------+-------+
|
||||
| DSPs | 0 | 0 | 90 | 0.00 |
|
||||
+-----------+------+-------+-----------+-------+
|
||||
|
||||
|
||||
4. IO and GT Specific
|
||||
---------------------
|
||||
|
||||
+-----------------------------+------+-------+-----------+-------+
|
||||
| Site Type | Used | Fixed | Available | Util% |
|
||||
+-----------------------------+------+-------+-----------+-------+
|
||||
| Bonded IOB | 26 | 0 | 210 | 12.38 |
|
||||
| Bonded IPADs | 0 | 0 | 2 | 0.00 |
|
||||
| PHY_CONTROL | 0 | 0 | 5 | 0.00 |
|
||||
| PHASER_REF | 0 | 0 | 5 | 0.00 |
|
||||
| OUT_FIFO | 0 | 0 | 20 | 0.00 |
|
||||
| IN_FIFO | 0 | 0 | 20 | 0.00 |
|
||||
| IDELAYCTRL | 0 | 0 | 5 | 0.00 |
|
||||
| IBUFDS | 0 | 0 | 202 | 0.00 |
|
||||
| PHASER_OUT/PHASER_OUT_PHY | 0 | 0 | 20 | 0.00 |
|
||||
| PHASER_IN/PHASER_IN_PHY | 0 | 0 | 20 | 0.00 |
|
||||
| IDELAYE2/IDELAYE2_FINEDELAY | 0 | 0 | 250 | 0.00 |
|
||||
| ILOGIC | 0 | 0 | 210 | 0.00 |
|
||||
| OLOGIC | 0 | 0 | 210 | 0.00 |
|
||||
+-----------------------------+------+-------+-----------+-------+
|
||||
|
||||
|
||||
5. Clocking
|
||||
-----------
|
||||
|
||||
+------------+------+-------+-----------+-------+
|
||||
| Site Type | Used | Fixed | Available | Util% |
|
||||
+------------+------+-------+-----------+-------+
|
||||
| BUFGCTRL | 1 | 0 | 32 | 3.13 |
|
||||
| BUFIO | 0 | 0 | 20 | 0.00 |
|
||||
| MMCME2_ADV | 0 | 0 | 5 | 0.00 |
|
||||
| PLLE2_ADV | 0 | 0 | 5 | 0.00 |
|
||||
| BUFMRCE | 0 | 0 | 10 | 0.00 |
|
||||
| BUFHCE | 0 | 0 | 72 | 0.00 |
|
||||
| BUFR | 0 | 0 | 20 | 0.00 |
|
||||
+------------+------+-------+-----------+-------+
|
||||
|
||||
|
||||
6. Specific Feature
|
||||
-------------------
|
||||
|
||||
+-------------+------+-------+-----------+-------+
|
||||
| Site Type | Used | Fixed | Available | Util% |
|
||||
+-------------+------+-------+-----------+-------+
|
||||
| BSCANE2 | 0 | 0 | 4 | 0.00 |
|
||||
| CAPTUREE2 | 0 | 0 | 1 | 0.00 |
|
||||
| DNA_PORT | 0 | 0 | 1 | 0.00 |
|
||||
| EFUSE_USR | 0 | 0 | 1 | 0.00 |
|
||||
| FRAME_ECCE2 | 0 | 0 | 1 | 0.00 |
|
||||
| ICAPE2 | 0 | 0 | 2 | 0.00 |
|
||||
| PCIE_2_1 | 0 | 0 | 1 | 0.00 |
|
||||
| STARTUPE2 | 0 | 0 | 1 | 0.00 |
|
||||
| XADC | 0 | 0 | 1 | 0.00 |
|
||||
+-------------+------+-------+-----------+-------+
|
||||
|
||||
|
||||
7. Primitives
|
||||
-------------
|
||||
|
||||
+----------+------+---------------------+
|
||||
| Ref Name | Used | Functional Category |
|
||||
+----------+------+---------------------+
|
||||
| FDCE | 43 | Flop & Latch |
|
||||
| LUT2 | 41 | LUT |
|
||||
| OBUF | 24 | IO |
|
||||
| LUT6 | 18 | LUT |
|
||||
| FDRE | 17 | Flop & Latch |
|
||||
| CARRY4 | 10 | CarryLogic |
|
||||
| LUT4 | 9 | LUT |
|
||||
| LUT5 | 7 | LUT |
|
||||
| LUT3 | 5 | LUT |
|
||||
| LUT1 | 3 | LUT |
|
||||
| IBUF | 2 | IO |
|
||||
| FDSE | 1 | Flop & Latch |
|
||||
| BUFG | 1 | Clock |
|
||||
+----------+------+---------------------+
|
||||
|
||||
|
||||
8. Black Boxes
|
||||
--------------
|
||||
|
||||
+----------+------+
|
||||
| Ref Name | Used |
|
||||
+----------+------+
|
||||
|
||||
|
||||
9. Instantiated Netlists
|
||||
------------------------
|
||||
|
||||
+----------+------+
|
||||
| Ref Name | Used |
|
||||
+----------+------+
|
||||
|
||||
|
||||
12
test/test.runs/synth_1/vivado.jou
Normal file
12
test/test.runs/synth_1/vivado.jou
Normal file
@@ -0,0 +1,12 @@
|
||||
#-----------------------------------------------------------
|
||||
# Vivado v2018.1 (64-bit)
|
||||
# SW Build 2188600 on Wed Apr 4 18:40:38 MDT 2018
|
||||
# IP Build 2185939 on Wed Apr 4 20:55:05 MDT 2018
|
||||
# Start of session at: Thu Dec 19 03:42:19 2024
|
||||
# Process ID: 3132
|
||||
# Current directory: Z:/Storage/Schoolwork/DigitalLogic/test/test.runs/synth_1
|
||||
# Command line: vivado.exe -log t_date.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source t_date.tcl
|
||||
# Log file: Z:/Storage/Schoolwork/DigitalLogic/test/test.runs/synth_1/t_date.vds
|
||||
# Journal file: Z:/Storage/Schoolwork/DigitalLogic/test/test.runs/synth_1\vivado.jou
|
||||
#-----------------------------------------------------------
|
||||
source t_date.tcl -notrace
|
||||
BIN
test/test.runs/synth_1/vivado.pb
Normal file
BIN
test/test.runs/synth_1/vivado.pb
Normal file
Binary file not shown.
Reference in New Issue
Block a user