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2025-11-06 10:08:01 +08:00
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52
test/test.srcs/constrs_1/imports/Downloads/EX1.xdc Normal file
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set_property IOSTANDARD LVCMOS33 [get_ports {a_h1[7]}]
set_property IOSTANDARD LVCMOS33 [get_ports {a_h1[6]}]
set_property IOSTANDARD LVCMOS33 [get_ports {a_h1[5]}]
set_property IOSTANDARD LVCMOS33 [get_ports {a_h1[4]}]
set_property IOSTANDARD LVCMOS33 [get_ports {a_h1[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {a_h1[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {a_h1[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {a_h1[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {a_h2[7]}]
set_property IOSTANDARD LVCMOS33 [get_ports {a_h2[6]}]
set_property IOSTANDARD LVCMOS33 [get_ports {a_h2[5]}]
set_property IOSTANDARD LVCMOS33 [get_ports {a_h2[4]}]
set_property IOSTANDARD LVCMOS33 [get_ports {a_h2[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {a_h2[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {a_h2[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {a_h2[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {an[7]}]
set_property IOSTANDARD LVCMOS33 [get_ports {an[6]}]
set_property IOSTANDARD LVCMOS33 [get_ports {an[5]}]
set_property IOSTANDARD LVCMOS33 [get_ports {an[4]}]
set_property IOSTANDARD LVCMOS33 [get_ports {an[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {an[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {an[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {an[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports clk]
set_property IOSTANDARD LVCMOS33 [get_ports rst]
set_property PACKAGE_PIN P17 [get_ports clk]
set_property PACKAGE_PIN R15 [get_ports rst]
set_property PACKAGE_PIN B4 [get_ports {a_h1[7]}]
set_property PACKAGE_PIN A4 [get_ports {a_h1[6]}]
set_property PACKAGE_PIN A3 [get_ports {a_h1[5]}]
set_property PACKAGE_PIN B1 [get_ports {a_h1[4]}]
set_property PACKAGE_PIN A1 [get_ports {a_h1[3]}]
set_property PACKAGE_PIN B3 [get_ports {a_h1[2]}]
set_property PACKAGE_PIN B2 [get_ports {a_h1[1]}]
set_property PACKAGE_PIN D5 [get_ports {a_h1[0]}]
set_property PACKAGE_PIN D4 [get_ports {a_h2[7]}]
set_property PACKAGE_PIN E3 [get_ports {a_h2[6]}]
set_property PACKAGE_PIN D3 [get_ports {a_h2[5]}]
set_property PACKAGE_PIN F4 [get_ports {a_h2[4]}]
set_property PACKAGE_PIN F3 [get_ports {a_h2[3]}]
set_property PACKAGE_PIN E2 [get_ports {a_h2[2]}]
set_property PACKAGE_PIN D2 [get_ports {a_h2[1]}]
set_property PACKAGE_PIN H2 [get_ports {a_h2[0]}]
set_property PACKAGE_PIN G2 [get_ports {an[7]}]
set_property PACKAGE_PIN C2 [get_ports {an[6]}]
set_property PACKAGE_PIN C1 [get_ports {an[5]}]
set_property PACKAGE_PIN H1 [get_ports {an[4]}]
set_property PACKAGE_PIN G1 [get_ports {an[3]}]
set_property PACKAGE_PIN F1 [get_ports {an[2]}]
set_property PACKAGE_PIN E1 [get_ports {an[1]}]
set_property PACKAGE_PIN G6 [get_ports {an[0]}]

102
test/test.srcs/sources_1/imports/Downloads/OUT.v Normal file
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`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2024/12/16 18:19:13
// Design Name:
// Module Name: OUT
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module OUT(clk,rst,y,an,a_h1,a_h2);
input clk;
input rst;
input [3:0]y;
output reg[7:0]an;
output reg[7:0]a_h1,a_h2;
always @(posedge clk)
if(rst)
an<=0000_0001;
else begin
case(y)
4'b0000:begin an<=0000_0001;
a_h2<=8'b1101_1010;
end
4'b0001:begin an<={an[7:2],an[0],an[1]};
case(an)
1:a_h2<=8'b1111_1100;
2:a_h2<=8'b1101_1010;
endcase
end
4'b0010:begin an<={an[7:3],an[0],an[2:1]};
case(an)
1:a_h2<=8'b1101_1010;
2:a_h2<=8'b1111_1100;
4:a_h2<=8'b1101_1010;
endcase
end
4'b0011:begin an<={an[7:4],an[0],an[3:1]};
case(an)
1:a_h2<=8'b0110_0111;
2:a_h2<=8'b1101_1010;
4:a_h2<=8'b1111_1100;
8:a_h2<=8'b1101_1010;
endcase
end
4'b0100:begin an<={an[7:5],an[0],an[4:1]};
case(an)
1:a_h2<=8'b0110_0000;
2:a_h2<=8'b0110_0111;
4:a_h2<=8'b1101_1010;
8:a_h2<=8'b1111_1100;
16:a_h1<=8'b1101_1010;
endcase
end
4'b0101:begin an<={an[7:6],an[0],an[5:1]};
case(an)
1:a_h2<=8'b1101_1011;
2:a_h2<=8'b0110_0000;
4:a_h2<=8'b0110_0111;
8:a_h2<=8'b1101_1010;
16:a_h1<=8'b1111_1100;
32:a_h1<=8'b1101_1010;
endcase
end
4'b0110:begin an<={an[7],an[0],an[6:1]};
case(an)
1:a_h2<=8'b0110_0000;
2:a_h2<=8'b1101_1011;
4:a_h2<=8'b0110_0000;
8:a_h2<=8'b0110_0111;
16:a_h1<=8'b1101_1010;
32:a_h1<=8'b1111_1100;
64:a_h1<=8'b1101_1010;
endcase
end
4'b0111:begin an<={an[0],an[7:1]};
case(an)
1:a_h2<=8'b1011_1110;
2:a_h2<=8'b0110_0000;
4:a_h2<=8'b1101_1011;
8:a_h2<=8'b0110_0000;
16:a_h1<=8'b0110_0111;
32:a_h1<=8'b1101_1010;
64:a_h1<=8'b1111_1100;
128:a_h1<=8'b1101_1010;
endcase
end
endcase
end
endmodule

57
test/test.srcs/sources_1/imports/Downloads/slow.v Normal file
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`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2024/12/16 15:44:41
// Design Name:
// Module Name: slow
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module clk(clk,rst,clk_1HZ,clk_20kHZ);
input clk,rst;
output clk_1HZ,clk_20kHZ;
reg clk_1HZ,clk_20kHZ;
reg [25:0]counter1;
reg [11:0]counter20k;
parameter sys_clk=100_000_000;
parameter clk_out1=1;
parameter clk_out20k=20_000;
parameter max1=sys_clk/(2*clk_out1)-1;
parameter max20k=sys_clk/(2*clk_out20k)-1;
always@(posedge clk or posedge rst) begin
if(rst)begin
clk_1HZ<=0;
clk_20kHZ<=0;
counter1<=0;
counter20k<=0;
end
else
begin
if(counter20k==max20k)begin
clk_20kHZ<=~clk_20kHZ;
counter20k<=0;
end
else
counter20k<=(counter20k)+1;
if(counter1==max1)begin
clk_1HZ<=~clk_1HZ;
counter1<=0;
end
else
counter1<=(counter1)+1;
end
end
endmodule

137
test/test.srcs/sources_1/imports/Downloads/t_date.v Normal file
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`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2024/12/16 15:53:27
// Design Name:
// Module Name: t_date
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module t_date (
clk,
rst,
an,
a_h1,
a_h2
);
input clk, rst;
output reg [7:0] a_h1, a_h2;
output reg [7:0] an;
parameter y0=4'b0000,y1=4'b0001,y2=4'b0010,y3=4'b0011,
y4=4'b0100,y5=4'b0101,y6=4'b0110,y7=4'b0111;
reg [3:0] state_c, state_n;
wire clk_1HZ, clk_20kHZ;
clk U1 (
.clk(clk),
.rst(rst),
.clk_1HZ(clk_1HZ),
.clk_20kHZ(clk_20kHZ)
);
always @(posedge clk_1HZ or posedge rst)
if (rst) state_c <= y0;
else state_c <= state_n;
always @(state_c)
case (state_c)
y0: state_n = y1;
y1: state_n = y2;
y2: state_n = y3;
y3: state_n = y4;
y4: state_n = y5;
y5: state_n = y6;
y6: state_n = y7;
y7: state_n = y0;
endcase
always @(posedge clk_20kHZ)
if (rst) an <= 0000_0001;
else begin
case (state_c)
4'b0000: begin
an <= 0000_0001;
a_h2 <= 8'b1101_1010;
end
4'b0001: begin
an <= {an[7:2], an[0], an[1]};
case (an)
1: a_h2 <= 8'b1101_1010;
2: a_h2 <= 8'b1111_1100;
endcase
end
4'b0010: begin
an <= {an[7:3], an[0], an[2:1]};
case (an)
1: a_h2 <= 8'b1101_1010;
2: a_h2 <= 8'b1101_1010;
4: a_h2 <= 8'b1111_1100;
endcase
end
4'b0011: begin
an <= {an[7:4], an[0], an[3:1]};
case (an)
1: a_h2 <= 8'b1101_1010;
2: a_h2 <= 8'b0110_0111;
4: a_h2 <= 8'b1101_1010;
8: a_h2 <= 8'b1111_1100;
endcase
end
4'b0100: begin
an <= {an[7:5], an[0], an[4:1]};
case (an)
1: a_h2 <= 8'b1111_1100;
2: a_h2 <= 8'b0110_0000;
4: a_h2 <= 8'b0110_0111;
8: a_h2 <= 8'b1101_1010;
16: a_h1 <= 8'b1101_1010;
endcase
end
4'b0101: begin
an <= {an[7:6], an[0], an[5:1]};
case (an)
1: a_h2 <= 8'b1101_1010;
2: a_h2 <= 8'b1101_1011;
4: a_h2 <= 8'b0110_0000;
8: a_h2 <= 8'b0110_0111;
16: a_h1 <= 8'b1101_1010;
32: a_h1 <= 8'b1111_1100;
endcase
end
4'b0110: begin
an <= {an[7], an[0], an[6:1]};
case (an)
1: a_h2 <= 8'b0110_0111;
2: a_h2 <= 8'b0110_0000;
4: a_h2 <= 8'b1101_1011;
8: a_h2 <= 8'b0110_0000;
16: a_h1 <= 8'b1101_1010;
32: a_h1 <= 8'b1101_1010;
64: a_h1 <= 8'b1111_1100;
endcase
end
4'b0111: begin
an <= {an[0], an[7:1]};
case (an)
1: a_h2 <= 8'b0110_0000;
2: a_h2 <= 8'b1011_1110;
4: a_h2 <= 8'b0110_0000;
8: a_h2 <= 8'b1101_1011;
16: a_h1 <= 8'b1101_1010;
32: a_h1 <= 8'b0110_0000;
64: a_h1 <= 8'b1101_1010;
128: a_h1 <= 8'b1111_1100;
endcase
end
endcase
end
endmodule