31 lines
591 B
Verilog
31 lines
591 B
Verilog
`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Engineer:
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//
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// Create Date: 2024/09/23 23:52:50
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// Design Name:
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// Module Name: First
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// Project Name:
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// Target Devices:
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// Tool Versions:
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// Description:
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//
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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//////////////////////////////////////////////////////////////////////////////////
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module First(a,b,z);
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input a,b;
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output z;
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wire [2:0] z;
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assign z[0] = a&b;
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assign z[1] = a|b;
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assign z[2] = a^b;
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endmodule
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