48 lines
924 B
Verilog
48 lines
924 B
Verilog
`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Engineer:
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//
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// Create Date: 2024/10/18 21:44:02
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// Design Name:
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// Module Name: VotingMachine
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// Project Name:
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// Target Devices:
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// Tool Versions:
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// Description:
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//
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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//////////////////////////////////////////////////////////////////////////////////
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module VotingMachine(
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input wire [4:0] votes,
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output wire [6:0] seg1,
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output wire [6:0] seg2,
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output reg [3:0] seg_cs1,
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output reg [3:0] seg_cs2
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);
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wire [2:0] count;
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wire pass;
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CoreModule u1 (
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.votes(votes),
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.count(count),
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.pass(pass)
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);
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SegDisplayCtrl u2 (
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.count(count),
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.pass(pass),
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.seg1(seg1),
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.seg2(seg2)
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);
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always @(*) begin
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seg_cs1 = 4'b0001;
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seg_cs2 = 4'b0001;
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end
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endmodule
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