52 lines
1.3 KiB
Verilog
52 lines
1.3 KiB
Verilog
`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Engineer:
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//
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// Create Date: 2024/10/31 10:43:01
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// Design Name:
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// Module Name: calc
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// Project Name:
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// Target Devices:
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// Tool Versions:
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// Description:
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//
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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//////////////////////////////////////////////////////////////////////////////////
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module calc(
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input [3:0] data1,
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input [3:0] data2,
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input [4:0] type,
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input clk,
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output reg [4:0] result,
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output wire [6:0] seg,
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output reg [3:0] seg_cs
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);
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reg [4:0] stored_type = 5'b00000;
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wire [4:0] judge_result;
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wire [4:0] operation_result;
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judge run (.data1(data1), .data2(data2), .result(judge_result));
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always @(posedge clk) begin
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if (type != 5'b00000) stored_type <= type;
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end
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always @(*) begin
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case (stored_type)
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5'b10000: result = data1 + data2;
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5'b01000: result = data1 & data2;
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5'b00100: result = data1 | data2;
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5'b00010: result = data1 ^ data2;
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5'b00001: result = judge_result;
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default: result = 5'b00000;
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endcase
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seg_cs = (stored_type != 5'b00000) ? 4'b0001 : 4'b0000;
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end
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SegDisplayCtrl unit (.type(stored_type), .seg(seg));
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endmodule
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