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Small patch to supress a warning

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綾瀬桃桃
2025-06-18 18:25:46 +08:00
parent 4512c1ac87
commit 105a5c3b06
5 changed files with 8 additions and 7 deletions
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4
Hardware/LA32R.sim/sim_1/behav/xsim/webtalk.jou
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@@ -2,8 +2,8 @@
# Webtalk v2018.1 (64-bit) # Webtalk v2018.1 (64-bit)
# SW Build 2188600 on Wed Apr 4 18:40:38 MDT 2018 # SW Build 2188600 on Wed Apr 4 18:40:38 MDT 2018
# IP Build 2185939 on Wed Apr 4 20:55:05 MDT 2018 # IP Build 2185939 on Wed Apr 4 20:55:05 MDT 2018
# Start of session at: Wed Jun 18 18:14:22 2025 # Start of session at: Wed Jun 18 18:21:59 2025
# Process ID: 41168 # Process ID: 8708
# Current directory: D:/Schoolwork/ComputerComposition/LA32R/Hardware/LA32R.sim/sim_1/behav/xsim # Current directory: D:/Schoolwork/ComputerComposition/LA32R/Hardware/LA32R.sim/sim_1/behav/xsim
# Command line: wbtcv.exe -mode batch -source D:/Schoolwork/ComputerComposition/LA32R/Hardware/LA32R.sim/sim_1/behav/xsim/xsim.dir/cpu_tb_snapshot/webtalk/xsim_webtalk.tcl -notrace # Command line: wbtcv.exe -mode batch -source D:/Schoolwork/ComputerComposition/LA32R/Hardware/LA32R.sim/sim_1/behav/xsim/xsim.dir/cpu_tb_snapshot/webtalk/xsim_webtalk.tcl -notrace
# Log file: D:/Schoolwork/ComputerComposition/LA32R/Hardware/LA32R.sim/sim_1/behav/xsim/webtalk.log # Log file: D:/Schoolwork/ComputerComposition/LA32R/Hardware/LA32R.sim/sim_1/behav/xsim/webtalk.log

4
Hardware/LA32R.sim/sim_1/behav/xsim/webtalk_42736.backup.jou → Hardware/LA32R.sim/sim_1/behav/xsim/webtalk_35000.backup.jou
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@@ -2,8 +2,8 @@
# Webtalk v2018.1 (64-bit) # Webtalk v2018.1 (64-bit)
# SW Build 2188600 on Wed Apr 4 18:40:38 MDT 2018 # SW Build 2188600 on Wed Apr 4 18:40:38 MDT 2018
# IP Build 2185939 on Wed Apr 4 20:55:05 MDT 2018 # IP Build 2185939 on Wed Apr 4 20:55:05 MDT 2018
# Start of session at: Wed Jun 18 18:14:18 2025 # Start of session at: Wed Jun 18 18:21:55 2025
# Process ID: 42736 # Process ID: 35000
# Current directory: D:/Schoolwork/ComputerComposition/LA32R/Hardware/LA32R.sim/sim_1/behav/xsim # Current directory: D:/Schoolwork/ComputerComposition/LA32R/Hardware/LA32R.sim/sim_1/behav/xsim
# Command line: wbtcv.exe -mode batch -source D:/Schoolwork/ComputerComposition/LA32R/Hardware/LA32R.sim/sim_1/behav/xsim/xsim.dir/cpu_tb_snapshot/webtalk/xsim_webtalk.tcl -notrace # Command line: wbtcv.exe -mode batch -source D:/Schoolwork/ComputerComposition/LA32R/Hardware/LA32R.sim/sim_1/behav/xsim/xsim.dir/cpu_tb_snapshot/webtalk/xsim_webtalk.tcl -notrace
# Log file: D:/Schoolwork/ComputerComposition/LA32R/Hardware/LA32R.sim/sim_1/behav/xsim/webtalk.log # Log file: D:/Schoolwork/ComputerComposition/LA32R/Hardware/LA32R.sim/sim_1/behav/xsim/webtalk.log

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Hardware/LA32R.sim/sim_1/behav/xsim/xsim.dir/cpu_tb_snapshot/xsim.mem
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4
Hardware/LA32R.sim/sim_1/behav/xsim/xsim.jou
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@@ -2,8 +2,8 @@
# xsim v2018.1 (64-bit) # xsim v2018.1 (64-bit)
# SW Build 2188600 on Wed Apr 4 18:40:38 MDT 2018 # SW Build 2188600 on Wed Apr 4 18:40:38 MDT 2018
# IP Build 2185939 on Wed Apr 4 20:55:05 MDT 2018 # IP Build 2185939 on Wed Apr 4 20:55:05 MDT 2018
# Start of session at: Wed Jun 18 18:14:19 2025 # Start of session at: Wed Jun 18 18:21:56 2025
# Process ID: 2304 # Process ID: 43956
# Current directory: D:/Schoolwork/ComputerComposition/LA32R/Hardware/LA32R.sim/sim_1/behav/xsim # Current directory: D:/Schoolwork/ComputerComposition/LA32R/Hardware/LA32R.sim/sim_1/behav/xsim
# Command line: xsim.exe -log ..\..\..\..\..\simulation.log -mode tcl -source {xsim.dir/cpu_tb_snapshot/xsim_script.tcl} # Command line: xsim.exe -log ..\..\..\..\..\simulation.log -mode tcl -source {xsim.dir/cpu_tb_snapshot/xsim_script.tcl}
# Log file: D:/Schoolwork/ComputerComposition/LA32R/Hardware/LA32R.sim/sim_1/behav/xsim/../../../../../simulation.log # Log file: D:/Schoolwork/ComputerComposition/LA32R/Hardware/LA32R.sim/sim_1/behav/xsim/../../../../../simulation.log

3
Hardware/LA32R.srcs/sim_1/new/cpu_tb.v
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@@ -38,6 +38,7 @@ module cpu_tb;
// --- 信号声明 --- // --- 信号声明 ---
reg clk; // 时钟信号 reg clk; // 时钟信号
reg rst; // 复位信号 reg rst; // 复位信号
integer i; // 用于for循环的变量
// --- 实例化待测设计 (DUT - Design Under Test) --- // --- 实例化待测设计 (DUT - Design Under Test) ---
// 将cpu_top模块实例化为uut (unit under test) // 将cpu_top模块实例化为uut (unit under test)
@@ -72,7 +73,7 @@ module cpu_tb;
$display(" 仿真结束。最终寄存器状态如下: "); $display(" 仿真结束。最终寄存器状态如下: ");
$display("------------------------------------------------------------"); $display("------------------------------------------------------------");
// 使用循环遍历寄存器堆，并通过$display显示其值。注意hierarchical path的正确性。 // 使用循环遍历寄存器堆，并通过$display显示其值。注意hierarchical path的正确性。
for (integer i = 0; i < 32; i = i + 1) begin for (i = 0; i < 32; i = i + 1) begin
// 为了简化输出，仅显示值非零的寄存器。 // 为了简化输出，仅显示值非零的寄存器。
if (uut.u_reg_file.registers[i] != 32'h00000000) begin if (uut.u_reg_file.registers[i] != 32'h00000000) begin
$display("寄存器 R%0d: 0x%08h", i, uut.u_reg_file.registers[i]); $display("寄存器 R%0d: 0x%08h", i, uut.u_reg_file.registers[i]);