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Refactor: Update comments to Chinese and standardize.

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This commit updates all comments in Verilog source files, the Python assembler, and the batch run script to Chinese.

Key changes include:
- Verilog files (.v):
  - Header comments (Description, Features, Revision, Additional Comments) translated and updated.
  - Inline comments translated to Chinese.
  - Removed [FIX], [NEW] tags, incorporating relevant information into the comments.
- assembler.py:
  - Main docstring and inline comments translated to Chinese.
  - Removed [FIX] style tags, with details moved to a revision history in the docstring.
  - Ensured no functional code changes were made.
- run.bat:
  - All user-facing `echo` prompts translated to Chinese.
  - Comments (::) reviewed and standardized in Chinese.

The codebase's logic and functionality remain unchanged. This effort improves readability and maintainability for Chinese-speaking developers by providing comprehensive and standardized documentation directly within the code.

Co-authored-by: google-labs-jules[bot] <161369871+google-labs-jules[bot]@users.noreply.github.com>
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綾瀬桃桃
2025-06-18 18:07:21 +08:00
committed by GitHub
parent 621c973a4a
commit 4bc6285c41
11 changed files with 625 additions and 418 deletions
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101
Hardware/LA32R.srcs/sim_1/new/cpu_tb.v
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@@ -11,89 +11,90 @@
** Target Devices: Any
** Tool Versions: Vivado 2018.1
** Description:
** A self-checking testbench for the LA32R single-cycle CPU.
** - Generates clock and reset signals.
** - Instantiates the cpu_top module.
** - The instruction_memory module (instantiated within cpu_top) will load
** the machine code from "program.hex".
** - Monitors and displays the state of the PC and register file.
**
** 本文件是为LA32R单周期CPU设计的一个自校验测试平台 (testbench)。
** 主要功能包括：
** - 生成时钟 (clk) 和复位 (rst) 信号。
** - 实例化顶层CPU模块 (cpu_top)。
** - CPU内部的指令存储器模块将从 "program.hex" 文件加载机器码。
** - 监控并显示程序计数器 (PC) 和寄存器堆的状态，以供分析。
** Features:
** - 产生周期性的时钟信号。
** - 提供可控的复位序列，用于初始化CPU。
** - 实例化待测试的CPU顶层模块 (uut)。
** - 通过预设的仿真时间控制仿真流程。
** - 在仿真结束时，打印所有非零寄存器的最终状态。
** - 在每个时钟周期的下降沿（确保信号稳定后）显示关键信号，如PC值、当前指令和特定寄存器的值。
** Revision:
** Revision 0.01 - File Created
** Revision 0.01 - 文件创建及基本测试流程实现。
** Additional Comments:
** - Place this file and "program.hex" in the simulation directory.
**
** - 请确保此测试平台文件和包含机器码的 "program.hex" 文件位于Vivado仿真工作目录下。
** - "program.hex" 的路径在 `instruction_memory.v` 模块中指定。
*******************************************************************************/
`timescale 1ns / 1ps
module cpu_tb;
// --- 信号声明 (Signal Declarations) ---
reg clk;
reg rst;
// --- 信号声明 ---
reg clk; // 时钟信号
reg rst; // 复位信号
// --- 实例化待测设计 (Instantiate the Design Under Test) ---
// --- 实例化待测设计 (DUT - Design Under Test) ---
// 将cpu_top模块实例化为uut (unit under test)
cpu_top uut (
.clk(clk),
.rst(rst)
);
// --- 时钟生成器 (Clock Generator) ---
localparam CLK_PERIOD = 10; // 时钟周期为10ns (Clock period is 10ns)
// --- 时钟生成逻辑 ---
localparam CLK_PERIOD = 10; // 定义时钟周期为10纳秒
initial begin
clk = 0;
forever #(CLK_PERIOD / 2) clk = ~clk;
clk = 0; // 初始化时钟为0
forever #(CLK_PERIOD / 2) clk = ~clk; // 每半个周期翻转时钟信号，产生方波
end
// --- 仿真控制 (Simulation Control) ---
// --- 仿真控制和主程序流程 ---
initial begin
// 1. 复位CPU (Reset the CPU)
rst = 1;
#(CLK_PERIOD * 2); // 保持复位2个周期 (Hold reset for 2 cycles)
rst = 0;
// 1. 初始化并施加复位信号
rst = 1; // 断言复位信号
#(CLK_PERIOD * 2); // 保持复位状态持续2个时钟周期，以确保CPU完全复位
rst = 0; // 撤销复位信号，CPU开始正常执行
$display("------------------------------------------------------------");
$display(" CPU Simulation Started. Reset is released. ");
$display(" CPU仿真开始。复位信号已释放。 ");
$display("------------------------------------------------------------");
// 2. 运行一段时间后停止仿真
// Stop the simulation after a certain amount of time.
// The test program has an infinite loop at the end,
// so we need to manually stop the simulation.
#500; // 运行500ns (Run for 500ns)
// 2. 设定仿真运行时间后停止
// 由于测试程序末尾通常是无限循环，因此需要手动设置仿真停止时间。
#500; // 仿真运行500纳秒
// 3. 打印最终的寄存器状态
// Print the final state of the registers
// 3. 仿真结束前，打印寄存器堆的最终状态
$display("\n------------------------------------------------------------");
$display(" Simulation Finished. Final Register State: ");
$display(" 仿真结束。最终寄存器状态如下: ");
$display("------------------------------------------------------------");
// 使用$display来显示寄存器的值。注意路径需要正确。
// Use $display to show register values. Note the path must be correct.
// 使用循环遍历寄存器堆，并通过$display显示其值。注意hierarchical path的正确性。
for (integer i = 0; i < 32; i = i + 1) begin
// 检查寄存器值是否非零，以简化输出
// Check if register value is non-zero to simplify output
// 为了简化输出，仅显示值非零的寄存器。
if (uut.u_reg_file.registers[i] != 32'h00000000) begin
$display("Register R%0d: 0x%08h", i, uut.u_reg_file.registers[i]);
$display("寄存器 R%0d: 0x%08h", i, uut.u_reg_file.registers[i]);
end
end
$display("※Please note that registers with value zero are hidden.※");
$display("※请注意：值为零的寄存器已被隐藏，未在此处显示。※");
$display("------------------------------------------------------------");
$finish; // 结束仿真 (End simulation)
$finish; // 调用$finish系统任务来结束仿真过程
end
// --- 监控和显示 (Monitoring and Display) ---
// 在每个时钟周期的下降沿打印信息，确保所有信号稳定
// Display info at the falling edge of the clock to ensure all signals are stable.
// --- 信号监控和数据显示 ---
// 在每个时钟周期的下降沿采样并显示信息，以确保在该时刻所有待显示的信号值均已稳定。
always @(negedge clk) begin
if (!rst) begin
$display("Time: %0t ns | PC: 0x%08h | Instruction: 0x%08h | R4=0x%h R5=0x%h R6=0x%h",
$time,
uut.pc_out,
uut.instr,
uut.u_reg_file.registers[4],
uut.u_reg_file.registers[5],
uut.u_reg_file.registers[6]
if (!rst) begin //仅在非复位状态下显示
$display("时间: %0t ns | PC: 0x%08h | 指令: 0x%08h | R4=0x%h R5=0x%h R6=0x%h",
$time, // 当前仿真时间
uut.pc_out, // PC的当前值
uut.instr, // 当前PC指向的指令
uut.u_reg_file.registers[4], // R4寄存器的值
uut.u_reg_file.registers[5], // R5寄存器的值
uut.u_reg_file.registers[6] // R6寄存器的值
);
end
end