109 lines
3.8 KiB
Batchfile
109 lines
3.8 KiB
Batchfile
@echo off
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:: 设置窗口标题
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TITLE LA32R CPU Simulation Automation
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:: ============================================================================
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:: LA32R 单周期 CPU 自动化仿真脚本 (适配Vivado项目结构)
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::
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:: 功能:
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:: 1. 定义项目文件路径。
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:: 2. 在正确的仿真目录下清理、执行所有步骤。
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:: 3. 运行 Python 汇编器生成 program.hex (已修正工作目录)。
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:: 4. 编译、链接并运行仿真 (已修正脚本提前退出的问题)。
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::
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:: 使用方法:
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:: - 将此脚本放在项目的根目录下。
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:: - 确保 Vivado 的 bin 目录已添加到系统的 PATH 环境变量中。
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:: - 直接双击运行此脚本。
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:: ============================================================================
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:: --- 步骤 0: 定义项目路径 ---
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:: %~dp0 会获取脚本所在的目录，作为我们的项目根目录
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set "PROJECT_ROOT=%~dp0"
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set "SOFTWARE_DIR=%PROJECT_ROOT%Software"
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set "DESIGN_SRC_DIR=%PROJECT_ROOT%Hardware\LA32R.srcs\sources_1\new"
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set "SIM_SRC_DIR=%PROJECT_ROOT%Hardware\LA32R.srcs\sim_1\new"
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set "SIM_RUN_DIR=%PROJECT_ROOT%Hardware\LA32R.sim\sim_1\behav\xsim"
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echo Project Root: %PROJECT_ROOT%
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echo Simulation Run Directory: %SIM_RUN_DIR%
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echo.
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:: --- 准备工作：切换到仿真运行目录 ---
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:: 创建目录（如果不存在）并进入
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if not exist "%SIM_RUN_DIR%" ( mkdir "%SIM_RUN_DIR%" )
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cd /d "%SIM_RUN_DIR%"
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:: --- 步骤 1: 清理环境 ---
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echo [STEP 1] Cleaning up previous simulation files...
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if exist xsim.dir ( rd /s /q xsim.dir )
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if exist *.log ( del *.log )
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if exist *.jou ( del *.jou )
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if exist verilog_files.f ( del verilog_files.f )
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if exist webtalk*.xml ( del webtalk*.xml )
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if exist webtalk*.tcl ( del webtalk*.tcl )
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echo.
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:: --- 步骤 2: 运行Python汇编器 ---
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echo [STEP 2] Assembling test program...
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:: [FIX] 使用 pushd/popd 临时切换目录以保证python脚本的工作目录正确
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pushd "%SOFTWARE_DIR%"
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python assembler.py
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popd
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:: 检查 program.hex 是否成功生成
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if not exist "%SOFTWARE_DIR%\program.hex" (
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echo [ERROR] Failed to generate program.hex. Halting script.
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goto end
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)
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:: [FIX] 移除文件复制步骤，因为Verilog已配置为使用相对路径
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echo Assembly complete. Verilog will read program.hex from its relative path.
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echo.
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:: --- 步骤 3: 创建文件列表并编译Verilog ---
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echo [STEP 3] Creating file list and compiling Verilog sources...
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:: 创建一个文件列表，包含所有设计和仿真源文件的绝对路径
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(
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echo "%DESIGN_SRC_DIR%\data_memory.v"
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echo "%DESIGN_SRC_DIR%\instruction_memory.v"
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echo "%DESIGN_SRC_DIR%\alu.v"
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echo "%DESIGN_SRC_DIR%\pc.v"
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echo "%DESIGN_SRC_DIR%\imm_extender.v"
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echo "%DESIGN_SRC_DIR%\register_file.v"
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echo "%DESIGN_SRC_DIR%\control_unit.v"
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echo "%DESIGN_SRC_DIR%\cpu_top.v"
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echo "%SIM_SRC_DIR%\cpu_tb.v"
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) > verilog_files.f
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:: [FIX] 添加 'call' 命令确保执行后控制权返回脚本
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call xvlog -sv --work xil_defaultlib -f verilog_files.f
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if %errorlevel% neq 0 (
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echo [ERROR] Verilog compilation failed. Check xvlog.log for details.
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goto end
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)
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echo Verilog compilation successful.
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echo.
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:: --- 步骤 4: 链接和构建仿真快照 ---
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echo [STEP 4] Elaborating the design with xelab...
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:: [FIX] 添加 'call' 命令
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call xelab --debug typical --snapshot cpu_tb_snapshot xil_defaultlib.cpu_tb -log elaborate.log
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if %errorlevel% neq 0 (
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echo [ERROR] Design elaboration failed. Check elaborate.log for details.
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goto end
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)
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echo Design elaboration successful.
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echo.
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:: --- 步骤 5: 运行仿真 ---
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echo [STEP 5] Running simulation with xsim...
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echo ======================= SIMULATION OUTPUT START =======================
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:: [FIX] 添加 'call' 命令
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call xsim cpu_tb_snapshot --runall --log ..\..\..\..\..\simulation.log
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echo ======================== SIMULATION OUTPUT END ========================
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echo.
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:end
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echo Script finished. Press any key to exit.
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pause > nul
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