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This commit updates all comments in Verilog source files, the Python assembler, and the batch run script to Chinese. Key changes include: - Verilog files (.v): - Header comments (Description, Features, Revision, Additional Comments) translated and updated. - Inline comments translated to Chinese. - Removed [FIX], [NEW] tags, incorporating relevant information into the comments. - assembler.py: - Main docstring and inline comments translated to Chinese. - Removed [FIX] style tags, with details moved to a revision history in the docstring. - Ensured no functional code changes were made. - run.bat: - All user-facing `echo` prompts translated to Chinese. - Comments (::) reviewed and standardized in Chinese. The codebase's logic and functionality remain unchanged. This effort improves readability and maintainability for Chinese-speaking developers by providing comprehensive and standardized documentation directly within the code. Co-authored-by: google-labs-jules[bot] <161369871+google-labs-jules[bot]@users.noreply.github.com>
76 lines
3.5 KiB
Verilog
76 lines
3.5 KiB
Verilog
`timescale 1ns / 1ps
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/*******************************************************************************
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** Company: Nantong University
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** Engineer: あやせももこ
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**
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** Create Date: 2025-06-16
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** Design Name: LA32R Single Cycle CPU
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** Module Name: alu
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** Project Name: Computer Architecture Course Design
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** Target Devices: Any FPGA
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** Tool Versions: Vivado 2018.1
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** Description:
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** 本模块为LA32R CPU实现算术逻辑单元(ALU)。
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** 它负责执行CPU指令所规定的算术运算（如加法、减法）和逻辑运算（如与、或、或非）。
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** 同时，它也处理比较操作（如有符号小于、无符号小于）并产生相应的标志位。
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** Features:
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** - 支持加法、减法、与、或、或非等基本运算。
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** - 支持有符号小于比较 (SLT) 和无符号小于比较 (SLTU)。
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** - SLT 操作使用 $signed() 以确保对有符号数的正确比较。
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** - 输出运算结果以及零标志位和小于标志位。
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** Revision:
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** Revision 0.02 - 修正了SLT指令的实现，使用$signed()处理有符号比较，确保结果的正确性。
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** Revision 0.01 - 文件创建。
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** Additional Comments:
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** 无。
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*******************************************************************************/
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module alu (
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input wire [31:0] a, // 操作数A
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input wire [31:0] b, // 操作数B
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input wire [3:0] alu_op, // ALU操作控制信号
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output reg [31:0] result, // ALU运算结果
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output wire zero, // 零标志位，用于判断结果是否为零
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output wire lt // 小于标志位，用于BLT指令判断
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);
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// 定义ALU支持的各种操作码，使用localparam增强代码的可读性和可维护性
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localparam ALU_ADD = 4'b0000; // 加法操作
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localparam ALU_SUB = 4'b0001; // 减法操作
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localparam ALU_AND = 4'b0010; // 逻辑与操作
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localparam ALU_OR = 4'b0011; // 逻辑或操作
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localparam ALU_NOR = 4'b0100; // 逻辑或非操作
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localparam ALU_SLT = 4'b0101; // 有符号小于比较操作
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localparam ALU_SLTU = 4'b0110; // 无符号小于比较操作
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// 执行减法操作，结果存储在临时线网sub_result中
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wire [31:0] sub_result = a - b;
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// 执行有符号小于比较，使用$signed()确保对负数的正确处理
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wire slt_res = ($signed(a) < $signed(b));
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// 执行无符号小于比较
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wire sltu_res = (a < b);
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// ALU核心逻辑：根据alu_op输入选择执行相应的操作
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always @(*) begin
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case (alu_op)
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ALU_ADD: result = a + b; // 执行加法
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ALU_SUB: result = sub_result; // 执行减法
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ALU_AND: result = a & b; // 执行逻辑与
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ALU_OR: result = a | b; // 执行逻辑或
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ALU_NOR: result = ~(a | b); // 执行逻辑或非
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ALU_SLT: result = {31'b0, slt_res}; // 执行有符号小于比较，结果为0或1
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ALU_SLTU: result = {31'b0, sltu_res}; // 执行无符号小于比较，结果为0或1
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default: result = 32'hxxxxxxxx; // 默认行为：当alu_op无效时，输出不确定值
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endcase
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end
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// 零标志位(zero flag)的生成逻辑：当减法结果（通常用于比较指令）为全零时，zero置1
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assign zero = (sub_result == 32'h00000000);
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// 小于标志位(less than flag)的生成逻辑：直接使用有符号比较的结果slt_res
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assign lt = slt_res;
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endmodule |