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2025-11-06 09:35:54 +08:00
commit 07678f510c
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30
Exp2/Exp2.cache/wt/webtalk_pa.xml Normal file
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<?xml version="1.0" encoding="UTF-8" ?>
<document>
<!--The data in this file is primarily intended for consumption by Xilinx tools.
The structure and the elements are likely to change over the next few releases.
This means code written to parse this file will need to be revisited each subsequent release.-->
<application name="pa" timeStamp="Mon Jun 9 00:51:56 2025">
<section name="Project Information" visible="false">
<property name="ProjectID" value="a73c9123352543f9bfb3406843b0bfb0" type="ProjectID"/>
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<property name="SynthesisStrategy" value="Vivado Synthesis Defaults" type="SynthesisStrategy"/>
<property name="ImplStrategy" value="Vivado Implementation Defaults" type="ImplStrategy"/>
</item>
<item name="Gui Handlers">
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</document>

34
Exp2/Exp2.srcs/sources_1/new/DR.v Normal file
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`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2025/05/30 19:43:40
// Design Name:
// Module Name: DR
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module DR (
input wire [31:0] Datain,
input wire clk,
input wire WE,
output reg [31:0] DataOut
);
always @(posedge clk) begin
if (WE) begin
DataOut <= Datain;
end
end
endmodule

43
Exp2/Exp2.srcs/sources_1/new/PC.v Normal file
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`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2025/05/30 20:48:55
// Design Name:
// Module Name: PC
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module PC (
input wire rst,
input wire clk,
input wire [31:0] offset,
input wire pc_inc,
output reg [31:0] PCdata
);
always @(posedge clk or posedge rst) begin
if (rst) begin
PCdata <= 32'h00000000;
end
else begin
if (pc_inc) begin
PCdata <= PCdata + 1;
end
else begin
PCdata <= PCdata + offset;
end
end
end
endmodule

37
Exp2/Exp2.srcs/sources_1/new/RAM.v Normal file
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`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2025/05/30 20:50:37
// Design Name:
// Module Name: RAM
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module RAM (
input wire clk,
input wire MemWrEn,
input wire [31:0] addr,
input wire [31:0] data_in,
output wire [31:0] data_out
);
reg [31:0] memory_array [2^32-1:0];
always @(posedge clk) begin
if (MemWrEn) begin
memory_array[addr] <= data_in;
end
end
assign data_out = memory_array[addr];
endmodule

41
Exp2/Exp2.srcs/sources_1/new/Registers.v Normal file
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`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2025/05/30 20:49:51
// Design Name:
// Module Name: Registers
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Registers (
input wire clk,
input wire RegWr,
input wire [4:0] Ra,
input wire [4:0] Rb,
input wire [4:0] Rw,
input wire [31:0] busW,
output wire [31:0] busA,
output wire [31:0] busB
);
reg [31:0] register_file [31:0];
always @(posedge clk) begin
if (RegWr && (Rw != 5'b00000)) begin
register_file[Rw] <= busW;
end
end
assign busA = (Ra == 5'b00000) ? 32'h00000000 : register_file[Ra];
assign busB = (Rb == 5'b00000) ? 32'h00000000 : register_file[Rb];
endmodule

162
Exp2/Exp2.xpr Normal file
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<?xml version="1.0" encoding="UTF-8"?>
<!-- Product Version: Vivado v2018.1 (64-bit) -->
<!-- -->
<!-- Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. -->
<Project Version="7" Minor="36" Path="D:/Schoolwork/ComputerComposition/Exp2/Exp2.xpr">
<DefaultLaunch Dir="$PRUNDIR"/>
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<Option Name="ProjectType" Val="Default"/>
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<Option Name="GenerateIPUpgradeLog" Val="TRUE"/>
<Option Name="XSimRadix" Val="hex"/>
<Option Name="XSimTimeUnit" Val="ns"/>
<Option Name="XSimArrayDisplayLimit" Val="1024"/>
<Option Name="XSimTraceLimit" Val="65536"/>
<Option Name="SimTypes" Val="rtl"/>
</Configuration>
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<Filter Type="Srcs"/>
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<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
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<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/new/PC.v">
<FileInfo>
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</Config>
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<Filter Type="Constrs"/>
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<Option Name="ConstrsType" Val="XDC"/>
</Config>
</FileSet>
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<Config>
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<Option Name="TopLib" Val="xil_defaultlib"/>
<Option Name="TopAutoSet" Val="TRUE"/>
<Option Name="TransportPathDelay" Val="0"/>
<Option Name="TransportIntDelay" Val="0"/>
<Option Name="SrcSet" Val="sources_1"/>
</Config>
</FileSet>
</FileSets>
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<Option Name="Description" Val="Vivado Simulator"/>
<Option Name="CompiledLib" Val="0"/>
</Simulator>
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<Option Name="Description" Val="ModelSim Simulator"/>
</Simulator>
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<Option Name="Description" Val="Questa Advanced Simulator"/>
</Simulator>
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<Option Name="Description" Val="Riviera-PRO Simulator"/>
</Simulator>
<Simulator Name="ActiveHDL">
<Option Name="Description" Val="Active-HDL Simulator"/>
</Simulator>
</Simulators>
<Runs Version="1" Minor="10">
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7a35tcsg324-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2018">
<Desc>Vivado Synthesis Defaults</Desc>
</StratHandle>
<Step Id="synth_design"/>
</Strategy>
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2018"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
</Run>
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7a35tcsg324-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true">
<Strategy Version="1" Minor="2">
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</StratHandle>
<Step Id="init_design"/>
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</Run>
</Runs>
<Board/>
</Project>