Initial commit

Exp2/Exp2.srcs/sources_1/new/DR.v

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+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date: 2025/05/30 19:43:40
+// Design Name: 
+// Module Name: DR
+// Project Name: 
+// Target Devices: 
+// Tool Versions: 
+// Description: 
+// 
+// Dependencies: 
+// 
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+// 
+//////////////////////////////////////////////////////////////////////////////////
+
+
+module DR (
+    input  wire [31:0] Datain,
+    input  wire        clk,
+    input  wire        WE,
+    output reg  [31:0] DataOut
+);
+    always @(posedge clk) begin
+        if (WE) begin
+            DataOut <= Datain;
+        end
+    end
+endmodule

Exp2/Exp2.srcs/sources_1/new/PC.v

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+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date: 2025/05/30 20:48:55
+// Design Name: 
+// Module Name: PC
+// Project Name: 
+// Target Devices: 
+// Tool Versions: 
+// Description: 
+// 
+// Dependencies: 
+// 
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+// 
+//////////////////////////////////////////////////////////////////////////////////
+
+
+module PC (
+    input  wire        rst,
+    input  wire        clk,
+    input  wire [31:0] offset,
+    input  wire        pc_inc,
+    output reg  [31:0] PCdata
+);
+    always @(posedge clk or posedge rst) begin
+        if (rst) begin
+            PCdata <= 32'h00000000;
+        end
+        else begin
+            if (pc_inc) begin
+                PCdata <= PCdata + 1;
+            end
+            else begin
+                PCdata <= PCdata + offset;
+            end
+        end
+    end
+endmodule

Exp2/Exp2.srcs/sources_1/new/RAM.v

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+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date: 2025/05/30 20:50:37
+// Design Name: 
+// Module Name: RAM
+// Project Name: 
+// Target Devices: 
+// Tool Versions: 
+// Description: 
+// 
+// Dependencies: 
+// 
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+// 
+//////////////////////////////////////////////////////////////////////////////////
+
+
+module RAM (
+    input  wire        clk,
+    input  wire        MemWrEn,
+    input  wire [31:0] addr,
+    input  wire [31:0] data_in,
+    output wire [31:0] data_out
+);
+    reg [31:0] memory_array [2^32-1:0];
+    always @(posedge clk) begin
+        if (MemWrEn) begin
+            memory_array[addr] <= data_in;
+        end
+    end
+    assign data_out = memory_array[addr];
+endmodule

Exp2/Exp2.srcs/sources_1/new/Registers.v

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+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date: 2025/05/30 20:49:51
+// Design Name: 
+// Module Name: Registers
+// Project Name: 
+// Target Devices: 
+// Tool Versions: 
+// Description: 
+// 
+// Dependencies: 
+// 
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+// 
+//////////////////////////////////////////////////////////////////////////////////
+
+
+module Registers (
+    input  wire        clk,
+    input  wire        RegWr,
+    input  wire [4:0]  Ra,
+    input  wire [4:0]  Rb,
+    input  wire [4:0]  Rw,
+    input  wire [31:0] busW,
+    output wire [31:0] busA,
+    output wire [31:0] busB
+);
+    reg [31:0] register_file [31:0];
+    always @(posedge clk) begin
+        if (RegWr && (Rw != 5'b00000)) begin
+            register_file[Rw] <= busW;
+        end
+    end
+    assign busA = (Ra == 5'b00000) ? 32'h00000000 : register_file[Ra];
+    assign busB = (Rb == 5'b00000) ? 32'h00000000 : register_file[Rb];
+endmodule